On Wed, Nov 29, 2017 at 5:43 AM, Jernej Škrabec wrote:
> Hi!
>
> Dne torek, 28. november 2017 ob 21:55:50 CET je Maxime Ripard napisal(a):
>> On Mon, Nov 27, 2017 at 09:57:46PM +0100, Jernej Skrabec wrote:
>> > DE2 have many CSC units - channel input CSC, channel output
Hi!
Dne torek, 28. november 2017 ob 21:55:50 CET je Maxime Ripard napisal(a):
> On Mon, Nov 27, 2017 at 09:57:46PM +0100, Jernej Skrabec wrote:
> > DE2 have many CSC units - channel input CSC, channel output CSC and
> > mixer output CSC and maybe more.
> >
> > Fortunately, they have all same
Hi Stefan,
On Mon, Nov 27, 2017 at 02:03:51PM +0200, Stefan Mavrodiev wrote:
> There will be option with 16MB flash for the following boards:
>
> * A20-OLinuXino-MICRO Rev.K
> * A20-OLinuXino-LIME Rev.J
> * A20-OLinuXino-LIME2 Rev.J
> * A20-SOM-EVB Rev.E
>
> The used flash chip is
Hi!
Dne torek, 28. november 2017 ob 22:00:01 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:41PM +0100, Jernej Skrabec wrote:
> > This commit adds basic support for VI planes. They are meant for video
> > overlay and because of that they support YUV formats too.
Hi,
On Mon, Nov 27, 2017 at 09:57:41PM +0100, Jernej Skrabec wrote:
> This commit adds basic support for VI planes. They are meant for video
> overlay and because of that they support YUV formats too. However, using
> YUV planes is not straightforward, so only RGB support for now.
>
>
On Mon, Nov 27, 2017 at 09:57:46PM +0100, Jernej Skrabec wrote:
> DE2 have many CSC units - channel input CSC, channel output CSC and
> mixer output CSC and maybe more.
>
> Fortunately, they have all same register layout, only base offsets
> differs.
>
> Add support only for channel output CSC
On Mon, Nov 27, 2017 at 09:57:45PM +0100, Jernej Skrabec wrote:
> Base addresses of channel output CSC (CCSC) depends whether mixer in
> question is first or second and if it is second, if supports VEP or not.
> This new property will tell which set of base addresses to take.
>
> 0 - first mixer
On Tue, Nov 28, 2017 at 08:02:26PM +0800, Icenowy Zheng wrote:
> 在 2017-11-28 04:57,Jernej Skrabec 写道:
> > Base addresses of channel output CSC (CCSC) depends whether mixer in
> > question is first or second and if it is second, if supports VEP or not.
> > This new property will tell which set of
On Mon, Nov 27, 2017 at 09:57:44PM +0100, Jernej Skrabec wrote:
> Calculate scaling parameters and call appropriate scaler set up
> function.
>
> Signed-off-by: Jernej Skrabec
I'm not sure there's been something wrong, but I didn't receive your
patch 10. I guess this
Hi,
On Mon, Nov 27, 2017 at 09:57:42PM +0100, Jernej Skrabec wrote:
> Scaler library currently supports scaling only RGB planes on VI planes.
>
> Coefficients and algorithm which ones to select are taken from BSP driver.
>
> Signed-off-by: Jernej Skrabec
> ---
>
Hi,
On Mon, Nov 27, 2017 at 09:57:43PM +0100, Jernej Skrabec wrote:
> No all SoCs support scaling on all channels. For example, V3s support
> scaling only on VI channels. Because of that, add additional
> configuration bitmask which tells which channel support scaler.
>
> Signed-off-by: Jernej
Hi,
On Mon, Nov 27, 2017 at 09:57:38PM +0100, Jernej Skrabec wrote:
> While DE2 driver works, parts of the code are not in optimal place. Reorder
> it so it will be easier to support multiple planes.
>
> This commit doesn't do any functional change besides removing two not
> very useful debug
On Mon, Nov 27, 2017 at 09:57:35PM +0100, Jernej Skrabec wrote:
> Till now, plane selection was hardcoded to first overlay in first UI
> channel.
>
> It turns out that overlays don't fit well in current DRM design, because
> they can't be blended together or scaled independetly when they are set
Hi!
Dne torek, 28. november 2017 ob 16:54:42 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:34PM +0100, Jernej Skrabec wrote:
> > Since the time initial DE2 driver was written, some knowledge was gained
> > what setting are really necessary and what most of the magic
On Tue, Nov 28, 2017 at 05:48:22PM +0100, Corentin Labbe wrote:
> The driver expect "allwinner,leds-active-low" to be in PHY node, but
> the binding doc expect it to be in MAC node.
>
> Since all board DT use it also in MAC node, the driver need to search
> allwinner,leds-active-low in MAC node.
The driver expect "allwinner,leds-active-low" to be in PHY node, but
the binding doc expect it to be in MAC node.
Since all board DT use it also in MAC node, the driver need to search
allwinner,leds-active-low in MAC node.
Signed-off-by: Corentin Labbe
---
Hi,
On Mon, Nov 27, 2017 at 09:57:34PM +0100, Jernej Skrabec wrote:
> Since the time initial DE2 driver was written, some knowledge was gained
> what setting are really necessary and what most of the magic values
> mean.
>
> This commit renames some of the macro names to better fit the real
>
Hi,
On Tue, Nov 28, 2017 at 03:51:14PM +0100, Thomas van Kleef wrote:
> On 28-11-17 13:26, Maxime Ripard wrote:
> > On Tue, Nov 28, 2017 at 12:20:59PM +0100, Thomas van Kleef wrote:
> >>> So, I have been rebasing to 4.14.0 and have the cedrus driver working.
> >> I have pulled linux-mainline
Il 28/11/2017 16:17, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017 at 02:12:31PM +0100, Giulio Benetti wrote:
And really, just develop against 4.14. sunxi-next is rebased, and it's
just not something you can base some work on.
Where do we can work on then?
Should Thomas setup his own github
On Tue, Nov 28, 2017 at 02:12:31PM +0100, Giulio Benetti wrote:
> > > > And really, just develop against 4.14. sunxi-next is rebased, and it's
> > > > just not something you can base some work on.
> > >
> > > Where do we can work on then?
> > > Should Thomas setup his own github repo?
> > > What
Il 28/11/2017 14:07, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017 at 02:03:43PM +0100, Giulio Benetti wrote:
Hi,
Il giorno 28 nov 2017, alle ore 13:52, Maxime Ripard
ha scritto:
On Tue, Nov 28, 2017 at 12:54:08PM +0100, Giulio Benetti wrote:
Should I be
On Tue, Nov 28, 2017 at 02:03:43PM +0100, Giulio Benetti wrote:
> Hi,
>
> > Il giorno 28 nov 2017, alle ore 13:52, Maxime Ripard
> > ha scritto:
> >
> > On Tue, Nov 28, 2017 at 12:54:08PM +0100, Giulio Benetti wrote:
> > Should I be working in sunxi-next I
Hi,
> Il giorno 28 nov 2017, alle ore 13:52, Maxime Ripard
> ha scritto:
>
> On Tue, Nov 28, 2017 at 12:54:08PM +0100, Giulio Benetti wrote:
> Should I be working in sunxi-next I wonder?
Yes, this is the best way, cedrus is very specific to
On Tue, Nov 28, 2017 at 12:54:08PM +0100, Giulio Benetti wrote:
> > > > Should I be working in sunxi-next I wonder?
> > >
> > > Yes, this is the best way, cedrus is very specific to sunxi.
> > > So before working on mainline, I think the best is to work un sunxi-next
> > > branch.
> >
> > Is the
On Tue, Nov 28, 2017 at 12:20:59PM +0100, Thomas van Kleef wrote:
> > So, I have been rebasing to 4.14.0 and have the cedrus driver working.
> I have pulled linux-mainline 4.14.0. Then pulled the requests2 branch from
> Hans
> Verkuil's media_tree. I have a patch available of the merge between
Hi,
On Tue, Nov 28, 2017 at 07:06:14PM +0800, Icenowy Zheng wrote:
> Allwinner H6 SoC has two pin controllers like other Allwinner SoCs with
> ARISC: one main pin controller (called CPUX-PORT in user manual) and one
> pin controller in the CPUs power domain (called CPUS-PORT in user
> manual).
>
Hi,
On Tue, Nov 28, 2017 at 05:26:37PM +0800, Chen-Yu Tsai wrote:
> On Tue, Nov 28, 2017 at 4:43 PM, Maxime Ripard
> wrote:
> > Hi,
> >
> > On Tue, Nov 28, 2017 at 12:12:11PM +0800, Chen-Yu Tsai wrote:
> >> The Libre Computer Board ALL-H3-CC from Libre
在 2017-11-28 04:57,Jernej Skrabec 写道:
Base addresses of channel output CSC (CCSC) depends whether mixer in
question is first or second and if it is second, if supports VEP or
not.
This new property will tell which set of base addresses to take.
0 - first mixer or second mixer with VEP support
Hi Thomas,
Il 28/11/2017 12:29, Thomas van Kleef ha scritto:
Hi,
On 28-11-17 12:26, Giulio Benetti wrote:
Hi Thomas,
Il 28/11/2017 12:20, Thomas van Kleef ha scritto:
On 28-11-17 10:50, Giulio Benetti wrote:
Hi Maxime,
Il 28/11/2017 09:35, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017
Hi Thomas,
Il 28/11/2017 12:20, Thomas van Kleef ha scritto:
On 28-11-17 10:50, Giulio Benetti wrote:
Hi Maxime,
Il 28/11/2017 09:35, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017 at 01:03:59AM +0100, Giulio Benetti wrote:
Hi Maxime,
Il 16/11/2017 14:42, Giulio Benetti ha scritto:
Hi,
在 2017-11-28 12:12,Chen-Yu Tsai 写道:
The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
Pi B+ form factor single board computer based on the Allwinner H3 SoC.
The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting
holes
and connectors are in the exact same
Allwinner H6 SoC has two pin controllers like other Allwinner SoCs with
ARISC: one main pin controller (called CPUX-PORT in user manual) and one
pin controller in the CPUs power domain (called CPUS-PORT in user
manual).
This commit adds support for the main pin controller in the H6 SoC.
Hi Maxime,
Il 28/11/2017 09:35, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017 at 01:03:59AM +0100, Giulio Benetti wrote:
Hi Maxime,
Il 16/11/2017 14:42, Giulio Benetti ha scritto:
Hi,
Il 16/11/2017 14:39, Maxime Ripard ha scritto:
On Thu, Nov 16, 2017 at 02:17:08PM +0100, Giulio Benetti
On Tue, Nov 28, 2017 at 4:43 PM, Maxime Ripard
wrote:
> Hi,
>
> On Tue, Nov 28, 2017 at 12:12:11PM +0800, Chen-Yu Tsai wrote:
>> The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
>> Pi B+ form factor single board computer based on the
Hi,
On Tue, Nov 28, 2017 at 12:12:11PM +0800, Chen-Yu Tsai wrote:
> The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
> Pi B+ form factor single board computer based on the Allwinner H3 SoC.
> The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes
> and
On Tue, Nov 28, 2017 at 01:03:59AM +0100, Giulio Benetti wrote:
> Hi Maxime,
>
> Il 16/11/2017 14:42, Giulio Benetti ha scritto:
> > Hi,
> >
> > Il 16/11/2017 14:39, Maxime Ripard ha scritto:
> > > On Thu, Nov 16, 2017 at 02:17:08PM +0100, Giulio Benetti wrote:
> > > > Hi Hans,
> > > >
> > > >
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