[linux-sunxi] [PATCH v2 5/6] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its memory map fully reworked and some high-speed peripherals (PCIe, USB 3.0) introduced. This commit adds the basical DTSI file of it, including the clock support and UART support. Signed-off-by: Icenowy Zheng

[linux-sunxi] [PATCH v2 6/6] arm64: allwinner: h6: add support for Pine H64 board

Pine H64 is an Allwinner H6-based SBC from Pine64, with the following features: - 1GiB/2GiB/4GiB LPDDR3 DRAM (in 4GiB situation only 3GiB is accessible) - AXP805 PMIC - Raspberry-Pi-compatible GPIO header, "Euler" GPIO header (not compatible with the "Euler" on Pine A64) and "Expansion" pin

[linux-sunxi] [PATCH v2 4/6] clk: sunxi-ng: add support for the Allwinner H6 CCU

The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng --- Changes in v2: - Exported APB1 bus clock for PIO. - Switch to SPDX license identifier.

[linux-sunxi] [PATCH v2 3/6] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks

On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng --- No changes in v2. drivers/clk/sunxi-ng/ccu_nkmp.c | 20

[linux-sunxi] [PATCH v2 2/6] pinctrl: sunxi: add support for the Allwinner H6 main pin controller

The Allwinner H6 SoC has two pin controllers, one main controller (called CPUX-PORT in user manual) and one controller in CPUs power domain (called CPUS-PORT in user manual). This commit introduces support for the main pin controller on H6. The pin bank A and B are not wired out and hidden from

[linux-sunxi] [PATCH v2 1/6] pinctrl: sunxi: support pin controllers with holes among IRQ banks

The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. This situation cannot be processed with the current pinctrl IRQ code, as it only expects a offset to all IRQ banks. Update the code to use a logical IRQ bank to

[linux-sunxi] [PATCH v2 0/6] Initial Allwinner H6 support

This patchset adds initial support for the Allwinner H6 SoC. It's quite different from earlier Allwinner SoCs. For example, the memory map is refactored, and the CCU is rearranged. It's also the first Allwinner SoC with PCI Express interface, and the second one with USB 3.0 (the first one is

[linux-sunxi] [PATCH] Revert "ARM: dts: sunxi: Add regulators for Sinovoip BPI-M2"

This reverts commit 7daa213700758b5b08fc0daab09bb139dd334165. The original commit has several problems: - vdd-cpus and aldo3 (AVCC of the SoC) are not set to always-on, which leads to system hang when disabling unused regulators. - GMAC (which uses dldo1 and aldo2) and Wi-Fi (which uses aldo1)

Re: [linux-sunxi] [RFC PATCH 8/8] sunxi: enable PSCI for A83T SoC

Hello! First of all I would like to thank you all for your amazing contribution! More I dive into understanding the kernel, more I appreciate your work and more I learn. As Marc Zyngier said: "Now, if someone could try and run guests on this turd and report whether this works correctly or