Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC"
pin, which is the VCC of HDMI part.
Add a supply property to specify HVCC's regulator in the device tree.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rename the supply name to "hvcc".
Changes in v3.1:
- New patch.
Docum
From: Jagan Teki
Enable all necessary device tree nodes and add connector node to device
trees for all supported A64 boards with HDMI.
Signed-off-by: Jagan Teki
[Icenowy: squash all board patches altogether and change supply name]
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rebase some d
From: Jernej Skrabec
Some boards have HDMI VCC pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
HDMI driver.
Signed-off-by: Jernej Skrabec
[Icenowy: change supply name to "hvcc"]
Signed-off-by: Ic
From: Jagan Teki
Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
TCON is connected to LCD and the second is to HDMI.
The HDMI controller/PHY pair is similar to the one on H3/H5.
Add all required device tree nodes of the display pipeline, including
the TCON0 LCD one and the
From: Jagan Teki
Mixers in Allwinner have similar capabilities as others SoCs with DE2.
Add support for them.
Signed-off-by: Jagan Teki
[Icenowy: Add mixer1]
Signed-off-by: Icenowy Zheng
Reviewed-by: Jernej Skrabec
---
Changes for v4:
- none
Changes for v3.1:
- Add mixer0
Changes for v3:
- n
From: Jagan Teki
The HDMI controller on Allwinner A64 is similar on the one on
H3/H5/A83T (although the PHY is different with A83T).
Add A64 compatible and append A83T compatible as fallback.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
[Icenowy: refactor commit log]
Signed-off-by: Icen
From: Jagan Teki
Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
The routing for mixer1 is through tcon1 and connected to HDMI.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy Zheng
---
Cha
From: Jagan Teki
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.
Include the macro on dt-bindings so-that the same can be used
while defining CCU clock phandles.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Dropped PLL_VIDEO1
From: Jagan Teki
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy Zheng
Reviewed
From: Jagan Teki
Allwinner A64 has a DE2 display pipeline. The TCONs are similar to the
ones in A83T, but the mixers are new (similar to the later R40 SoC).
This patch adds dt-binding documentation for A64 DE2 display pipeline.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
[Icenowy: Refa
Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.
Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, user manual specifies maximum frequency to
be 600 MHz. Historically, this data was wrong in some user manuals for
ot
Allwinner A64 has display engine pipeline like other Allwinner SOC's A83T/H3/H5.
A64 behaviour similar to Allwinner A83T where
Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
Mixer1 => TCON1 => HDMI
as per Display System Block Diagram from the A64 user manual.
This patchset adds support for the two display
On 02.09.2018 22:01, Jonathan Cameron wrote:
On Thu, 30 Aug 2018 17:44:53 +0200
Philipp Rossak wrote:
We are moving the SUN4I_GPADC_CHANNEL define to the header file.
Maxime has raised this point in other patches...
Why? Obvious what but I have no idea why you are doing this.
Thanks,
Jona
On 02.09.2018 22:11, Jonathan Cameron wrote:
This feels like a good place to factor out the code into a utility
function that just does one of them. That should hopefully
reduce the indenting etc enough to make the code easier to read.
+ info->tzds[i].info = info;
+
The A64 HDMI PHY is proven to have no PLL-VIDEO mux, thus it's not
compatible with the R40 one.
Drop the A64 fallback compatible string in R40 device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arc
By experiment, the A64 HDMi PHY doesn't support the PLL-VIDEO mux
introduced in R40, although it has two PLL-VIDEOs.
Change the A64 HDMI PHY binding to R40 one.
This binding is introduced in v4.19, which is still in RC stage, so we
have change to fix it.
Signed-off-by: Icenowy Zheng
---
.../de
The Allwinner A64 SoC is proven to have no PLL-VIDEO mux in the HDMI PHY
clock, although it has two PLL-VIDEOs. The R40 SoC has this mux.
Change the binding compatible string from sun50i-a64 to sun8i-r40, and
let A64 to use H3 compatible string.
The compatible string is introduced in v4.19, and d
It is used to be believed that the A64 HDMI PHY has the PLL-VIDEO mux
which is introduced in R40, because A64 has two PLL-VIDEOs. However,
experiments show that the mux is not present in A64, so the compatible
string of dual-PLL-input HDMI PHY clock must be changed to use R40 in
it rather than A64.
Hi,
On 03-09-18 14:42, Maxime Ripard wrote:
On Mon, Sep 03, 2018 at 12:01:52PM +0200, Corentin Labbe wrote:
This patchset add support for allwinner R40 AHCI controller.
The whole patchset is tested on sun8i-r40-bananapi-m2-ultra and
on sun7i-a20-cubieboard2 which doesnt have any of the ressour
On Mon, Sep 03, 2018 at 12:01:52PM +0200, Corentin Labbe wrote:
> This patchset add support for allwinner R40 AHCI controller.
>
> The whole patchset is tested on sun8i-r40-bananapi-m2-ultra and
> on sun7i-a20-cubieboard2 which doesnt have any of the ressources added
> by this serie, so no regress
hi,
On Sun, Sep 02, 2018 at 09:26:26AM +0200, Jernej Skrabec wrote:
> H6 is first Allwinner SoC which supports 10 bit colors, HDR and AFBC.
>
> Signed-off-by: Jernej Skrabec
> ---
> drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/sun4i
于 2018年9月3日 GMT+08:00 下午6:20:22, Maxime Ripard 写到:
>On Fri, Aug 31, 2018 at 05:51:41PM +0800, Icenowy Zheng wrote:
>> Personally I suggest to leave out all SID or calibration related
>> patches here.
>>
>> Currently we seems to be wrongly converting SID to big endian,
>however,
>> the orgnizat
On Fri, Aug 31, 2018 at 05:51:41PM +0800, Icenowy Zheng wrote:
> Personally I suggest to leave out all SID or calibration related
> patches here.
>
> Currently we seems to be wrongly converting SID to big endian, however,
> the orgnization of the THS calibration data on H6 shows that it's
> surely
R40 have a sata controller which is the same as A20.
This patch adds a DT node for it.
Signed-off-by: Icenowy Zheng
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-r40.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/b
This patch update binding with the new R40 compatible.
Signed-off-by: Corentin Labbe
---
Documentation/devicetree/bindings/ata/ahci-platform.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt
b/Documentation/devicetree/bindings/ata/
This patch enable the AHCI controller.
Since this controller need two regulator, this patch add them.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m
The SoC R40 AHCI controller need a PHY regulator to work.
But since the PHY is embedded in the controller, we cannot do a DT node for it,
since phy-supply works only in node with a PHY compatible.
So this patch adds a way to add an optional phy-supply regulator on AHCI
controller node.
Signed-off
This patch document the new optional phy-supply.
Signed-off-by: Corentin Labbe
---
Documentation/devicetree/bindings/ata/ahci-platform.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt
b/Documentation/devicetree/bindings/ata/ahci-pla
This patch add the r40 compatible to the ahci_sunxi's supported list of
compatible.
Since R40 need ahci_platform to handle the reset controller, we also add
the new AHCI_PLATFORM_GET_RESETS flag for ahci_platform_get_resources().
This has no consequence for older platform (a10, a20) since the rese
This patch document the new optional ahci-supply.
Signed-off-by: Corentin Labbe
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/ata/ahci-platform.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt
b/Documentation/devic
This patch fix the indentation of target-supply's ':'.
Signed-off-by: Corentin Labbe
---
Documentation/devicetree/bindings/ata/ahci-platform.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt
b/Documentation/devicetree
This patchset add support for allwinner R40 AHCI controller.
The whole patchset is tested on sun8i-r40-bananapi-m2-ultra and
on sun7i-a20-cubieboard2 which doesnt have any of the ressources added
by this serie, so no regression should come with it.
Patchs 1-7 should go via the ata tree
Patchs 8,9
The SoC R40 AHCI controller need a regulator to work.
So this patch add a way to add an optional regulator on AHCI controller.
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci.h | 1 +
drivers/ata/libahci_platform.c | 26 --
2 files changed, 25 insertions(+
On Fri, Aug 31, 2018 at 02:05:59PM +0200, Philipp Rossak wrote:
>
>
> On 31.08.2018 11:09, Maxime Ripard wrote:
> > > +static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info)
> > suspend is already a hook in the kernel, which hasn't the same meaning
> > than runtime_suspend (and the same appli
On 08/28/2018 10:02 AM, Paul Kocialkowski wrote:
> This introduces the required definitions for HEVC decoding support with
> stateless VPUs. The controls associated to the HEVC slice format provide
> the required meta-data for decoding slices extracted from the bitstream.
>
> This interface comes
On 08/28/2018 09:34 AM, Paul Kocialkowski wrote:
> This introduces the Cedrus VPU driver that supports the VPU found in
> Allwinner SoCs, also known as Video Engine. It is implemented through
> a v4l2 m2m decoder device and a media device (used for media requests).
> So far, it only supports MPEG2
This looks very nice. I have two more comments, but they can be added using
a follow-up patch (unless you need a v9 anyway):
On 08/28/2018 09:34 AM, Paul Kocialkowski wrote:
> Stateless video decoding engines require both the MPEG slices and
> associated metadata from the video stream in order to
On Fri, Aug 31, 2018 at 08:35:23AM -0600, Jens Axboe wrote:
> On 8/31/18 1:40 AM, Maxime Ripard wrote:
> > Hi Jens,
11;rgb:/2b2b/3636> >
> > On Thu, Aug 30, 2018 at 08:52:52PM -0600, Jens Axboe wrote:
> >> On 8/30/18 8:32 PM, Chen-Yu Tsai wrote:
> >>> Hi,
> >>>
> >>> On Fri, Aug 31, 2018 at 4:
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