On Mon, 26 Nov 2018 00:22:03 +0800, Hao Zhang wrote:
> The clock source for sun8i R40 is from apb1, so export it for
> dt parses.
>
> Signed-off-by: Hao Zhang
> ---
> drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 4 +++-
> include/dt-bindings/clock/sun8i-r40-ccu.h | 2 ++
> 2 files changed, 5
Hi!
Dne sreda, 05. december 2018 ob 10:24:44 CET je Paul Kocialkowski napisal(a):
> This adds the Video Engine node for the A64. Since it can map the whole
> DRAM range, there is no particular need for a reserved memory node
> (unlike platforms preceding the A33).
>
> Signed-off-by: Paul
Hello all.
Attached are my u-boot .config and modified device tree files targeting my
modified Orange Pi Win Plus board. The board in question has a 16GB eMMC
soldered on it.
Here is a dump of an interrupted boot process:
> U-Boot SPL 2018.11 (Dec 08 2018 - 03:06:29 +0800)
> DRAM: 2048 MiB
>
On 02/12/2018 20:23, Mesih Kilinc wrote:
> This is the sixth version of patchset for Allwinner ARMv5 F1C100s
> SoC. Addressed comments from Stephen Boyd, added signatures.
I've queued the 4 irqchip patches for 4.21.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
--
You
On Wed, Nov 21, 2018 at 11:35 PM Priit Laes wrote:
>
> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3" series,
> posted by Olliver Schinagl in March 2017. Unfortunately it never got past
> initial discussion [1], but most Olimex Lime2 boards are still running
> into this bug.
From: Ondrej Jirman
When parallel bus is used and data-active is being parsed, incorrect
flags are cleared.
Clear the correct flag bits.
Fixes: e9be1b863e2c2948deb003df8edd9635b4611a8a (media: v4l: fwnode:
Use default parallel flags).
Signed-off-by: Ondrej Jirman
---
On Tue, Nov 27, 2018 at 04:34:35PM +0530, Jagan Teki wrote:
> On Tue, Nov 27, 2018 at 3:55 PM Maxime Ripard
> wrote:
> >
> > On Tue, Nov 20, 2018 at 09:55:42PM +0530, Jagan Teki wrote:
> > > On Tue, Nov 20, 2018 at 9:27 PM Maxime Ripard
> > > wrote:
> > > >
> > > > On Thu, Nov 15, 2018 at
On Tue, Dec 4, 2018 at 10:05 AM Chen-Yu Tsai wrote:
> Pin PH11 is used on various A83T board to detect a change in the OTG
> port's ID pin, as in when an OTG host cable is plugged in.
>
> The incorrect offset meant the gpiochip/irqchip was activating the wrong
> pin for interrupts.
>
> Fixes:
On Mon, Dec 3, 2018 at 4:41 PM Chen-Yu Tsai wrote:
> This small series renames the csi0 and ts0 pin function names to csi and
> ts. This makes the names match the datasheet. As there are only one of
> each type of controller, having a numeral suffix doesn't make sense.
>
> I'd like to do the
