[linux-sunxi] Re: [PATCH v2] sunxi: clock: H6/H616: Fix PLL clock factor encodings

2021-05-26 Thread Andre Przywara
On Wed, 5 May 2021 13:53:05 +0100 Andre Przywara wrote: Hi, > Most clock factors and dividers in the H6 PLLs use a "+1 encoding", > which we were missing on two occasions. can someone please confirm that I didn't mess this up? Cheers, Andre > > This fixes the MMC clock setup on the H6,

[linux-sunxi] Re: [PATCH v2 4/6] net: sun8i-emac: add v3s variant

2021-05-26 Thread Andre Przywara
On Sun, 23 May 2021 01:22:38 +0200 Andreas Rehn wrote: Hi, > Add variant V3S_EMAC. > Handle pinmux compile time error by skipping goio setup, because > V3s uses internal phy and don't expose pins. > > Signed-off-by: Andreas Rehn Reviewed-by: Andre Przywara Cheers, Andre > --- > Changes in

[linux-sunxi] Re: [PATCH v2 3/6] clk: sunxi: v3s: fix tabs / spaces

2021-05-26 Thread Andre Przywara
On Sun, 23 May 2021 01:17:29 +0200 Andreas Rehn wrote: > align CLK_USB_PHY0 with tabs > > Signed-off-by: Andreas Rehn Reviewed-by: Andre Przywara Cheers, Andre P.S. Please send a whole v2 series next time, to make this easier to sort out which patch still applies and which not. > --- >

[linux-sunxi] Re: [PATCH v5 02/16] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes

2021-05-26 Thread Paul Kocialkowski
Hi everyone, On Fri 15 Jan 21, 21:01, Paul Kocialkowski wrote: > As some D-PHY controllers support both Rx and Tx mode, we need a way for > users to explicitly request one or the other. For instance, Rx mode can > be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI. > >

[linux-sunxi] Re: [PATCH v5 00/16] Allwinner MIPI CSI-2 support for A31/V3s/A83T

2021-05-26 Thread Paul Kocialkowski
Hi, On Wed 26 May 21, 14:00, Hans Verkuil wrote: > Hi Paul, > > On 15/01/2021 21:01, Paul Kocialkowski wrote: > > This series introduces support for MIPI CSI-2, with the A31 controller that > > is > > found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific > > controller.

[linux-sunxi] Re: [PATCH v5 00/16] Allwinner MIPI CSI-2 support for A31/V3s/A83T

2021-05-26 Thread Hans Verkuil
Hi Paul, On 15/01/2021 21:01, Paul Kocialkowski wrote: > This series introduces support for MIPI CSI-2, with the A31 controller that is > found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific > controller. While the former uses the same MIPI D-PHY that is already > supported

[linux-sunxi] Re: [PATCH v5 02/16] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes

2021-05-26 Thread Paul Kocialkowski
Hi, On Wed 26 May 21, 13:50, Hans Verkuil wrote: > On 15/01/2021 21:01, Paul Kocialkowski wrote: > > As some D-PHY controllers support both Rx and Tx mode, we need a way for > > users to explicitly request one or the other. For instance, Rx mode can > > be used along with MIPI CSI-2 while Tx mode

[linux-sunxi] Re: [PATCH v5 02/16] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes

2021-05-26 Thread Hans Verkuil
On 15/01/2021 21:01, Paul Kocialkowski wrote: > As some D-PHY controllers support both Rx and Tx mode, we need a way for > users to explicitly request one or the other. For instance, Rx mode can > be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI. > > Introduce new MIPI D-PHY

Re: [linux-sunxi] alternate irc network -> OFTC

2021-05-26 Thread Luc Verhaegen
On Sat, May 22, 2021 at 09:43:37PM +0200, Luc Verhaegen wrote: > On Fri, May 21, 2021 at 10:01:12PM +0200, Luc Verhaegen wrote: > > All existing and active founders/operators (mnemoc, turl, plaes, rellla, > libv) were moved. And two new ones (wens, apritzel) were added. > > Whitelogger has now