Hi,
On 09/01/20 3:24 PM, Corentin Labbe wrote:
> Hello
>
> On next-20200108 (at least), the sunxi_ahci fail to probe with:
> 3.025955] 8<--- cut here ---
> [3.029012] Unable to handle kernel NULL pointer dereference at virtual
> address 0071
> [3.037115] pgd = (ptrval)
> [
Hi,
On 24/10/19 4:24 PM, Ondrej Jirman wrote:
> From: Icenowy Zheng
>
> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> controlled).
>
> Add a driver for it.
>
> The register operations in this driver is mainly extracted from the BSP
> USB3 driver.
>
> Signed-off-by:
On 15/04/19 4:47 PM, Paul Kocialkowski wrote:
> Hi,
>
> Le jeudi 14 mars 2019 à 14:05 +0100, Paul Kocialkowski a écrit :
>> On platforms where the MUSB and HCI controllers share PHY0, PHY passby
>> is required when using the HCI controller with the PHY, but it must be
>> disabled when the MUSB
Hi,
On 14/11/18 10:27 AM, Icenowy Zheng wrote:
在 2018-10-04四的 20:28 +0800,Icenowy Zheng写道:
Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
controlled).
Add a driver for it.
The register operations in this driver is mainly extracted from the
BSP
USB3 driver.
Signed-off-by:
On 02/11/18 2:11 PM, Icenowy Zheng wrote:
> 在 2018-10-04四的 20:28 +0800,Icenowy Zheng写道:
>> The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner
>> SoCs,
>> with some USB0 quirk like A83T and PHY index 1/2 missing.
>>
>> Add support for it.
>>
>> Signed-off-by: Icenowy Zheng
>>
Hi,
On Thursday 15 March 2018 11:47 AM, Chen-Yu Tsai wrote:
> Hi Kishon,
>
> On Fri, Feb 16, 2018 at 7:20 PM, Kishon Vijay Abraham I wrote:
>>
>>
>> On Friday 19 January 2018 08:15 PM, Maxime Ripard wrote:
>>> On Fri, Jan 19, 2018 at 05:25:41PM +0800, Chen-Yu Tsai wrote:
The
On Friday 19 January 2018 08:15 PM, Maxime Ripard wrote:
> On Fri, Jan 19, 2018 at 05:25:41PM +0800, Chen-Yu Tsai wrote:
>> The AXP223 PMIC, like the AXP221, does not generate VBUS change
>> interrupts when N_VBUSEN is used to drive VBUS for the OTG port
>> on the board.
>>
>> This was not
On Friday 19 January 2018 01:43 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 19 January 2018 11:55 AM, Chen-Yu Tsai wrote:
>> Hi Kishon,
>>
>> On Mon, Jan 15, 2018 at 11:06 PM, Hermann Lauer
>> wrote:
>>> On Wed, Jan 03, 2018 at 04:49:44PM +0800,
Hi,
On Friday 19 January 2018 11:55 AM, Chen-Yu Tsai wrote:
> Hi Kishon,
>
> On Mon, Jan 15, 2018 at 11:06 PM, Hermann Lauer
> wrote:
>> On Wed, Jan 03, 2018 at 04:49:44PM +0800, Icenowy Zheng wrote:
>>> Allwinner R40 features a USB PHY like the one in A64,
Hi,
On Saturday 30 December 2017 05:08 PM, Icenowy Zheng wrote:
> 在 2017年10月18日星期三 CST 下午7:46:08,Kishon Vijay Abraham I 写道:
>> On Wednesday 18 October 2017 05:12 PM, Maxime Ripard wrote:
>>> On Wed, Oct 18, 2017 at 05:09:00PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 10
Hi,
On Tuesday 10 October 2017 02:28 AM, Maxime Ripard wrote:
> On Sun, Oct 08, 2017 at 04:29:01AM +, Icenowy Zheng wrote:
>> Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
>>
>> Add support for it.
>>
>> Signed-off-by: Icenowy Zheng
>
> Acked-by:
Hi Icenowy,
On Thursday 28 September 2017 09:03 PM, Maxime Ripard wrote:
> On Thu, Sep 28, 2017 at 09:58:59AM +, icen...@aosc.io wrote:
>> 在 2017-09-28 17:47,Maxime Ripard 写道:
>>> On Thu, Sep 28, 2017 at 09:33:48AM +, Icenowy Zheng wrote:
Allwinner V3s SoC has only one USB PHY, but
Hi,
On Thursday 17 August 2017 10:35 PM, Chen-Yu Tsai wrote:
> On Fri, Aug 11, 2017 at 1:08 AM, Rob Herring wrote:
>> On Thu, Aug 03, 2017 at 04:14:04PM +0800, Chen-Yu Tsai wrote:
>>> The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
>>> regions, clocks, resets,
On Thursday 03 August 2017 01:44 PM, Chen-Yu Tsai wrote:
> The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
> regions, clocks, resets, and optional vbus properties. These were
> not described when the H3 compatible string was added.
>
> Fixes: 626a630e003c ("phy-sun4i-usb: Add
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