"txco"] is still considered invalid, but it's
> generally considered as a best practice to fix the order of clocks.
>
> Cc: "David S. Miller"
> Cc: Jakub Kicinski
> Cc: Linus Walleij
> Cc: net...@vger.kernel.org
> Reviewed-by: Rob Herring
> Signed-off-by
se that require
> exactly two interrupts, even though it might not make sense on those
> devices or in some setups.
>
> Let's remove the clause entirely.
>
> Cc: Denis Ciocca
> Cc: Jonathan Cameron
> Cc: Lars-Peter Clausen
> Cc: Linus Walleij
> Cc: linux-...@vger.ker
On Mon, Jan 18, 2021 at 3:09 AM Andre Przywara wrote:
> There are only two pins left now, used to connect to the PMIC via I2C.
>
> Signed-off-by: Andre Przywara
> Acked-by: Maxime Ripard
> Reviewed-by: Jernej Skrabec
Patch applied to the pinctrl tree.
Yours,
Linus Walleij
-
rl tree.
Yours,
Linus Walleij
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On Mon, Jan 18, 2021 at 3:09 AM Andre Przywara wrote:
> A new SoC, a new compatible string.
> Also we were too miserly with just allowing seven interrupt banks.
>
> Signed-off-by: Andre Przywara
Patch applied to the pinctrl tree.
Yours,
Linus Walleij
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no
> primary function 2 given. This suggests the primary function for these
> pins is actually RSB, and that is indeed the case.
>
> Add the "s_rsb" pin functions so the RSB controller can be used.
>
> Signed-off-by: Samuel Holland
This patch applied to the pinctrl t
no
> primary function 2 given. This suggests the primary function for these
> pins is actually RSB, and that is indeed the case.
>
> Add the "s_rsb" pin functions so the RSB controller can be used.
>
> Signed-off-by: Samuel Holland
Is it OK if I just apply this patch to
No DT binding changes needed?
Yours,
Linus Walleij
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To view t
ply clean on top of drm-misc-next - due to
> > vrefresh removal.
> > Please re-spin.
>
> Sorry for that. Rebased and retested.
Sam will you apply it? I was in the middle of applying and ran into the same
issue :D
Yours,
Linus Walleij
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On Fri, Jun 26, 2020 at 2:56 AM Ondrej Jirman wrote:
> Pinephone has a Goodix GT917S capacitive touchscreen controller on
> I2C0 bus. Add support for it.
>
> Signed-off-by: Ondrej Jirman
Acked-by: Linus Walleij
Yours,
Linus Walleij
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> Signed-off-by: Icenowy Zheng
> Signed-off-by: Martijn Braam
> Signed-off-by: Ondrej Jirman
Acked-by: Linus Walleij
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On Fri, Jun 26, 2020 at 2:56 AM Ondrej Jirman wrote:
> The reset pin is inverted, so if we don't assert reset, the actual gpio
> will be high and may keep driving the IO port of the panel.
>
> Signed-off-by: Ondrej Jirman
Reviewed-by: Linus Walleij
Yours,
Linus Walleij
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On Fri, Jun 26, 2020 at 2:56 AM Ondrej Jirman wrote:
> The datasheet suggests to issue sleep in after display off
> as a part of the panel's shutdown sequence.
>
> Signed-off-by: Ondrej Jirman
Reviewed-by: Linus Walleij
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Linus Walleij
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On Fri, Jun 26, 2020 at 2:56 AM Ondrej Jirman wrote:
> Xingbangda XBD599 is a 5.99" 720x1440 MIPI-DSI LCD panel used in
> PinePhone. Add support for it.
>
> Signed-off-by: Icenowy Zheng
> Signed-off-by: Ondrej Jirman
Reviewed-by: Linus Walleij
Yours,
Linus Walle
On Fri, Jun 26, 2020 at 2:56 AM Ondrej Jirman wrote:
> Calling sleep out and display on is a controller specific part
> of the initialization process. Move it out of the panel specific
> initialization function to the enable callback.
>
> Signed-off-by: Ondrej Jirman
Reviewed-by
On Fri, Jun 26, 2020 at 2:56 AM Ondrej Jirman wrote:
> It's better than having it spread around the driver.
>
> Signed-off-by: Ondrej Jirman
Reviewed-by: Linus Walleij
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On Fri, Jun 26, 2020 at 2:56 AM Ondrej Jirman wrote:
> Parametrize the driver so that it can support more panels based
> on st7703 controller.
>
> Signed-off-by: Ondrej Jirman
Reviewed-by: Linus Walleij
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Linus Walleij
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On Fri, Jun 26, 2020 at 2:56 AM Ondrej Jirman wrote:
> This is done so that code that's not specific to a particular
> jh057n panel is named after the controller. Functions specific
> to the panel are kept named after the panel.
>
> Signed-off-by: Ondrej Jirman
Reviewed-by
Signed-off-by: Ondrej Jirman
This is the right thing to do.
Reviewed-by: Linus Walleij
Yours,
Linus Walleij
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Further I wrote:
You should definately insert code to read the MTP bytes:
0xDA manufacturer
0xDB driver version
0xDC LCD module/driver
And print these, se e.g. my newly added NT35510 driver or
the Sony ACX424AKP driver.
So please do that.
Yours,
Linus Walleij
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off-by: Ondrej Jirman
Reviewed-by: Linus Walleij
Yours,
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probed.
> So don't say anything if the return code say to wait.
>
> Signed-off-by: Corentin Labbe
Patch applied with Maxime's ACK!
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Linus Walleij
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So following up on this:
We should state in the commit message that this driver is for all
displays using the Sitronix ST770x display controllers.
The driver should be named panel-sitronix-st770x.c.
On Thu, Mar 19, 2020 at 3:08 PM Linus Walleij wrote:
> > +/* Manufacturer specific Co
On Fri, Mar 20, 2020 at 9:07 AM Icenowy Zheng wrote:
> 于 2020年3月19日 GMT+08:00 下午10:14:27, Linus Walleij
> 写到:
> >On Mon, Mar 16, 2020 at 2:37 PM Icenowy Zheng wrote:
> >As noticed in the review of the driver, this display is very close to
> >himax,hx8363.
bindings
ilitek-ili9342.yaml and then:
properties:
compatible:
items:
- const: xingbangda,xbd599
- const: ilitek,ili9342
Possibly use oneOf and add support for the himax,hx8363
already while you're at it.
Yours,
Linus Walleij
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ink this vrefresh is going away soon.
> + .clock = 69000,
> + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
> +
> + .width_mm= 68,
> + .height_mm = 136,
> + .type= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> +};
All
vel
> via the IRQCHIP_MASK_ON_SUSPEND flag.
>
> Signed-off-by: Samuel Holland
Patch applied.
Yours,
Linus Walleij
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to the upper irqchip must also be enabled for wakeup. Since the
> kernel's IRQ core already manages the "wake_depth" of each IRQ, no
> additional accounting is needed in the pinctrl driver.
>
> Signed-off-by: Samuel Holland
Patch applied with Maxime's ACK.
Yours,
Linus Wall
needs
to be fixed properly.
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To vie
On Sun, Jul 28, 2019 at 5:13 AM Icenowy Zheng wrote:
> Introduce the GPIO pins that is only available on V3 (not on V3s) to the
> V3s pinctrl driver.
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Maxime Ripard
Patch applied to the pinctrl tree.
Ypurs,
Linus Walleij
-
/
> > + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
>
> I'm not sure why all that churn is needed.
>
> Looks good otherwise.
Should I apply the patch or wait for a new version without the
whit
e vendor prefix for SoChip.
>
> Signed-off-by: Icenowy Zheng
> Reviewed-by: Rob Herring
> ---
> No changes in v3.
>
> Changes in v2:
> - Add the review tag by Rob.
Should I apply this to the pinctrl tree? Rob?
Yours,
Linus Walleij
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patch.
Yours,
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off-by: Icenowy Zheng
> Reviewed-by: Rob Herring
> ---
> Changes in v2:
> - Add the review tag by Rob.
Patch applied.
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Linus Walleij
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me Ripard
> Reviewed-by: Rob Herring
> ---
> Changes in v2:
> - Add the ACK tag by Maxime and the review tag by Rob.
Patch applied to the pinctrl tree.
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mmit 402bfb3c1352 ("Support I/O bias voltage setting on A80")
>
> Signed-off-by: Ondrej Jirman
> Acked-by: Maxime Ripard
This patch applied to the pinctrl tree for v5.2.
Yours,
Linus Walleij
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This patch applied to the pinctrl tree for v5.2.
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actively ignored.
> */
Yeah this caused me special headache in the current merge
window because of buggy code on my part.
This is an effect of this flag being defined for powerpc
ages before we properly implemented generic GPIO
bindings. We just have to respect it.
See:
https://marc.i
happy with the patches?
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Linus Walleij
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uff into an immutable branch in the pinctrl tree so that it can
be pulled in to ARM SoC if need be (for DTS files to compile for example).
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mic changing of the I/O voltages.
>
> Signed-off-by: Chen-Yu Tsai
I merged the v5.0-rc6 into my devel branch and applied this patch on
top now.
All the DTS file changes should be merged through ARM SoC, and
they should work fine now.
Yours,
Linus Walleij
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s that I merge v5.0-rc6 as soon as it is
out and then try to apply this on top of that instead, so we get
rid of this conflict?
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upts.
>
> Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller
> support")
> Cc:
> Signed-off-by: Chen-Yu Tsai
Patch applied for fixes with Maxime's ACK.
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I'd like to do the rename now while we don't have users nor support for
> these two controllers. I planned to send this together with CSI support
> for the A64, but Jagan beat me to it, so here it is.
Patch applied with Maxime's ACK.
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Linus Walleij
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plied to the pin control tree for v4.21.
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On Sun, Nov 25, 2018 at 8:44 AM Mesih Kilinc wrote:
> Add compatible string for Allwinner suniv F1C100s SoC's pinctrl.
>
> Signed-off-by: Mesih Kilinc
> Acked-by: Maxime Ripard
Patch applied to the pin control tree for v4.21.
Yours,
Linus Walleij
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applied with the ACKs.
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For more op
rt for the Allwinner H6 main pin controller
I applied these pinctrl patches for v4.17 so anything dependent on that
can now be merged.
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y: Icenowy Zheng <icen...@aosc.io>
> Acked-by: Rob Herring <r...@kernel.org>
Patch applied with all the ACKs.
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nk map, in
> order to support the case that holes exist among IRQ banks.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
> ---
> Extracted in v4.
Patch applied with Maxime's ACK.
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his commit introduces a IRQ bank conversion function, which replaces
> the "(bank_base + bank)" code in IRQ register access.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
> ---
> Extracted in v4.
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
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> ---
> Changes in v4:
> - Adjusted parameter sequence.
Patch applied with Maxime's ACK.
Yours,
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st clock defined.
> Since named clocks can be in any order, let's explicitly check for a
> clock called "apb" if there is more than one clock referenced.
>
> Kudo to Maxime for suggesting this much more elegant approach.
>
> Signed-off-by: Andre Przywara <andre.przyw...@
s finished, I will
apply it after v4 if Maxime provides ACKs for it.
Is it fine to merge the pinctrl drivers/* portions in isolation from the
rest?
Yours,
Linus Walleij
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On Sat, Feb 3, 2018 at 4:49 PM, Icenowy Zheng <icen...@aosc.io> wrote:
> This patchset adds initial support for the Allwinner H6 SoC.
I see there are still a few comments from Maxime and André
so I'm waiting for a new patch set. I need their ACKs to proceed.
Yours,
Linus Walleij
On Mon, Jan 29, 2018 at 9:25 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Sat, Jan 27, 2018 at 05:14:26PM +0100, Linus Walleij wrote:
>> > +void sun6i_csi_update_buf_addr(struct sun6i_csi *csi, dma_addr_t addr)
>> > +{
>> > + struct su
s buffer which is coherent
in physical memory, or from some buffer <= 64KB that
is switching ownership between device and CPU explicitly
with dma_map* or so. Did you check with
Documentation/DMA-API.txt?
Yours,
Linus Walleij
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On Sat, Jan 6, 2018 at 5:18 AM, Icenowy Zheng <icen...@aosc.io> wrote:
> This patchset adds initial support for the Allwinner H6 SoC.
Can I apply the pin control patches without the clock patches?
Also waiting for Maxime and/or Chen-Yu to provide some review
before merging this.
You
("pinctrl: sunxi: add support of R40 to A10 pinctrl
> driver")
> Reported-by: Mark Kettenis <mark.kette...@xs4all.nl>
> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Patch applied.
Yours,
Linus Walleij
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: 23f75d7dfa92 ("pinctrl: axp209: add pinctrl features")
>
> Reported-by: Randy Dunlab <rdun...@infradead.org>
Fixed that name.
> Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Patch applied with Randy's ACK.
Yours,
Linus Walleij
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ser...@free-electrons.com>
Patch applied with the tags for test and ACK.
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rl_desc *)of_device_get_match_data(dev);
>
> Linus, I guess that I should send a patch to fix this or is there an
> other way not to have to apply such a small and dumb patch?
Just send a patch based on my pin control tree "devel" branch or
linux-next, it's cool.
Things like this happens all the ti
On Wed, Dec 6, 2017 at 1:55 AM, André Przywara <andre.przyw...@arm.com> wrote:
> On 01/12/17 09:56, Linus Walleij wrote:
>> It is a valid cause. Just
>> has to be weighed with other stuff, like maintainability, debuggability,
>> maintainers viewpoint. ...
>
> S
On Thu, Nov 30, 2017 at 5:07 PM, Andre Przywara <andre.przyw...@arm.com> wrote:
> On 30/11/17 15:51, Linus Walleij wrote:
>> On Sat, Nov 25, 2017 at 1:02 PM, Andre Przywara <andre.przyw...@arm.com>
>> wrote:
>>
>>> All of the H5 boards in the kernel refer
> - add a few information to the Kconfig to make checkpatch happy,
I have applied patches 1-8 to an immutable branch in the GPIO
tree, then merged that into the GPIO "devel" branch as well as the
pinctrl "devel" branch so we can develop the driver in the pinctrl
tree hencefo
t; I suggest patches 1 to 8 go through Linus's tree and 9 and 10 via Maxime or
> Chen-Yu's tree.
>
> v4:
Looks overall good. As soon as Maxime is happy with everything I will
happily apply 1-8 to the pinctrl tree and then pull it to GPIO as well to
avoid clashes.
I think there were some min
On Fri, Dec 1, 2017 at 2:44 PM, Quentin Schulz
<quentin.sch...@free-electrons.com> wrote:
> This adds DT node for the GPIO/pinctrl part present in AXP813/AXP818.
>
> Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Linus Walleij <linus.wall...@l
@free-electrons.com>
Acked-by: Linus Walleij <linus.wall...@linaro.org>
It doesn't seem to have any dependencies so I guess Lee can simply
apply this separately.
Yours,
Linus Walleij
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gs.txt
> +The GPIOs can be muxed to other functions and therefore, must be a subnode of
> +axp_gpio.
> +
> +Example:
> +
> +_gpio {
> + gpio0_adc: gpio0-adc {
> + pins = "GPIO0";
> + function = "adc";
> + };
&
de we need to add to
> support new SoCs.
This is the core of your argument as I perceive it: get rid of data
from the kernel, because it is growing wild. It is a valid cause. Just
has to be weighed with other stuff, like maintainability, debuggability,
maintainers viewpoint. ...
Yours,
Linus Wa
to have your way if you were submitting an entirely
new driver. Like this pinmux property, it was submitted by the
mediatek people because it fits their usecase/hardware especially
well.
Yours,
Linus Walleij
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n the H5 driver.
>
> Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
> Reported-by: Chris Obbard <obba...@gmail.com>
Patch applied with Maxime's ACK.
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Przywara <andre.przyw...@arm.com>
Patch applied with Chen-Yu's ACK and fixes tag.
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Linus Walleij
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k healthy (instead more like a copy bug from pins PA14-PA16),
> so fix the interrupt bank for pins PB14-PB16, which is actually 1.
>
> I don't have any A80 board, so could not test this.
>
> Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Patch applied with Chen-Yu's A
On Fri, Nov 24, 2017 at 1:05 PM, Andre Przywara <andre.przyw...@arm.com> wrote:
> On 24/11/17 10:28, Linus Walleij wrote:
>> The DT maintainers have been pretty clear on that they don't like
>> using the the DT as a generic fit-all information dump. They
>> prefer to
k's control, and we don't disrupt
> anything when the pin is requested.
In a way since setting the bits one way means "LDO on" and another
setting means "LDO off" those bits should be handled by the
regulator framework when used as a regulator, not pin control.
So I would
for some obscure reason connected
to the GPIO controller (!) instead, and the actual consumer of this state
is NOT the GPIO controller, but quite obviously the regulator, so
put the pinctrl business in that regulator node instead.
"default" mode is OK on a regulator, as that can be expected
series going, we merge once Maxime and Chen-Yu are happy.
Yours,
Linus Walleij
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e unintuitive and end
up wasting power because people will get confused about
what is going on.
Instead, call this state "regulator" and when using, in Linux
create a regulator device that set the pin into "regulator" state to
start using it as a LDO, and "default" t
> DT bits had been merged around v4.10.
>
> Signed-off-by: Priit Laes <pl...@plaes.org>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
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t;icen...@aosc.io>
Patch applied with Chen-Yu's ACK.
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bank base.
>
> Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC")
> Cc: sta...@vger.kernel.org
This patch only applies on the devel branch so I don't see why it is tagged
for stable.
> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Patch applied.
Yo
ot; for consistency.
>
> The "s_twi" functions are not yet referenced by any device trees in
> mainline kernel so I think it's safe to change the name.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Patch applied with Chen-Yu's review tag.
Yours,
Linus Walleij
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osc.io>
> Reviewed-by: Chen-Yu Tsai <w...@csie.org>
> ---
> Changes in v3:
Patch applied for next.
Yours,
Linus Walleij
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need to only fix the A10 driver now.
>
> Fixes: f2821b1ca3a2 ("pinctrl: sunxi: Move Allwinner A10 pinctrl
> driver to a driver of its own")
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
> Reviewed-by: Chen-Yu Tsai <w...@csie.org>
> ---
> Changes in v3
add a missing function of A10/A20 pinctrl driver
>> pinctrl: sunxi: add support of R40 to A10 pinctrl driver
>
>
> Ping...
>
> Can anyone process this patchset?
Sorry, I was on vacation.
Looking at the backlog now.
Yours,
Linus Walleij
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On Sat, Jun 3, 2017 at 4:44 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> The A83T has 1 pingroup with 13 pins belonging to the R_PIO
> or special pin controller.
>
> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Linus Walleij <linus.wall...@linaro.org>
Pls f
i <w...@csie.org>
Patch applied.
Yours,
Linus Walleij
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n-Yu Tsai <w...@csie.org>
Patch applied with Rob's ACK.
Yours,
Linus Walleij
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t;
> Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller
> support")
> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Patch applied for fixes with Maxime's ACK.
Yours,
Linus Walleij
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e: Add generic pinctrl functions
> for managing groups")
> Reported-by: Andre Przywara <andre.przyw...@arm.com>
> Signed-off-by: Tony Lindgren <t...@atomide.com>
Thanks! This nice inline patch applied for fixes with André's tags.
Yours,
Linus Walleij
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You received thi
fore
> R40 support is added into the A10 driver.
I'd be happy to merge the pinctrl parts as soon as you fixed the
things pointed out during review. Include Rob's ACKs on the
DT binding patches please.
Yours,
Linus Walleij
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an array with the
> indices" in the first place. If we can just call radix_tree_delete()
> directly from the radix_tree_for_each_slot() loop, we can have a much
> better fix (omitting the memory allocation at all)
OK I pulled the patch out again for now.
> Linus, can you shed
ht to me but I'm waiting for Maxime's review on these
patches.
Yours,
Linus Walleij
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2122-gc08bac03d289/arm64/defconfig/lab-baylibre-seattle/boot-sun50i-a64-pine64-plus.html
> ---
> Hi,
>
> not sure this is the right fix, I am open to suggestions.
I have queued this as a tentative v4.12-rc1 fix, but a bit undertain.
Tejun, do I read your comments on the patch as
es on this board
like in the other rpi boards, should be something like:
{
gpio-line-names = "...", "...";
};
This is very helpful for users.
Yours,
Linus Walleij
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ut we have fixed that! We can now select GPIOLIB
directly from any driver that needs it.
Yours,
Linus Walleij
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t
ed guess and
> try and error.
Out of curiosity: does the board support use the mainline drivers
as starting point? I.e. does it build on top of the community work done
by Maxime & others?
Yours,
Linus Walleij
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"linu
e happy to merge patches 1,2 & 3 to the pinctrl tree but I need
a maintainer ACK on these three patches first.
Yours,
Linus Walleij
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interrupt banks. (There's one more GPIO banks (PF) that can do
> interrupt handling on H5)
I already applied V2 with Maximes' ACK and all.
Yours,
Linus Walleij
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