Hi Oliver,
2017-03-01 13:52 GMT+01:00 Olliver Schinagl :
> +#define AXP209_VRC_LDO3_EN BIT(3)
> +#define AXP209_VRC_DCDC2_ENBIT(2)
> +#define AXP209_VRC_LDO3_800uV_uS (BIT(1) | AXP209_VRC_LDO3_EN)
> +#define AXP209_VRC_LDO3_1600uV_uS
2017-02-28 13:19 GMT+01:00 Lyubcho Haralanov :
> The question that really bugs me is: why toggling LDO4 doesn't affect the
> board but toggling LDO3 kills it...
>
Can you measure the time it takes LDO3 and LDO4 to ramp to up the their
final value? LDO4 seems to have a
Hi Lyubcho,
2017-02-27 15:36 GMT+01:00 Lyubcho Haralanov :
> VR1 is not assembled (NA). It is not placed. Only pads are provided in
> case you don't want to power the camera from the AXP209 but externally, in
> which case you should place VR1 and disconnect the SMT jumper
Hi,
2017-02-27 13:11 GMT+01:00 oliver :
> One is to remove C185 (10 microF) and the problem went away. Looking at
> other designs, cubieboard 1 for example, uses the same layout, but only 4.7
> microF. So it seems that charging of all the capacitance (input C106) the
> board
g it back on, then set it to the correct value afterwards. Or even
use a slightly higher staring voltage... 1,75V also seems to work reliably
my SOM, slightly higher values work sometimes, anything in the region of 2V
always shuts down the AXP.
Cheers,
Marcus
2017-02-26 13:35 GMT+01:00 Marcu
2017-02-26 13:19 GMT+01:00 Marcus Weseloh <mweselo...@gmail.com>:
> So when we switch on LDO3 and the AXP powers that rail, there are now two
> sources driving that line. Might be that the AXP notices this, maybe even
> sees current flowing into it's output, and shuts down imme
2017-02-26 11:31 GMT+01:00 Priit Laes :
> Could it be a layout/design issue with Olimex boards?
It may well be! Looking at the schematic of the A20-SOM-EVB (the base board
for the A20-SOM), it seems like the CSI interface is powered via the +5V
supply and converter to 2.8V. But
Hi Oliver,
2017-02-24 23:13 GMT+01:00 Olliver Schinagl :
> It turns out, turning on LDO3, after it was turned off before, causes the
> PMIC to shut down. Even enabeling all interrupts and checking the interrupt
> pin, nothing could be found as to why however. It is thus
Hi,
2016-01-17 19:51 GMT+01:00 Maxime Ripard <maxime.rip...@free-electrons.com>:
> On Sun, Jan 10, 2016 at 10:11:11PM +0100, Marcus Weseloh wrote:
>> >> >> - /* Ensure that we have a parent clock fast enough */
>> >> >> + /*
>> >>
Hi,
2016-01-13 12:18 GMT+01:00 Maxime Ripard <maxime.rip...@free-electrons.com>:
> Sorry for the reviewing delay.
No problem at all, thanks for the review!
> On Mon, Dec 28, 2015 at 06:31:32PM +0100, Marcus Weseloh wrote:
>> This patch fixes some problems in the mod0 clock c
Hi,
2016-01-10 19:14 GMT+01:00 Maxime Ripard <maxime.rip...@free-electrons.com>:
> On Mon, Dec 28, 2015 at 12:29:16AM +0100, Marcus Weseloh wrote:
>> 2015-12-27 22:09 GMT+01:00 Maxime Ripard <maxime.rip...@free-electrons.com>:
>> > On Sat, Dec 26, 2015 at 04:53:05
Hi,
2016-01-10 20:44 GMT+01:00 Maxime Ripard <maxime.rip...@free-electrons.com>:
> On Mon, Dec 28, 2015 at 05:22:35PM +0100, Marcus Weseloh wrote:
>> 2015-12-28 0:29 GMT+01:00 Marcus Weseloh <mweselo...@gmail.com>:
>> > 2015-12-27 22:09 GMT+01:00 Maxime Ri
runtime power-management on every transfer,
>> without it only on the first one):
>>
>> activate, deactivate, activate, transfer, deactivate
>>
>> Moving the configuration of the SUN4I_CTL_CS_MANUAL flag from transfer_one
>> to set_cs removes this problem.
>>
&g
Hi again,
2015-12-28 0:29 GMT+01:00 Marcus Weseloh <mweselo...@gmail.com>:
> 2015-12-27 22:09 GMT+01:00 Maxime Ripard <maxime.rip...@free-electrons.com>:
[...]
> [...]
>>> - /* Ensure that we have a parent clock fast enough */
>>> + /*
>>>
Hi,
2015-12-27 22:09 GMT+01:00 Maxime Ripard <maxime.rip...@free-electrons.com>:
> On Sat, Dec 26, 2015 at 04:53:05PM +0100, Marcus Weseloh wrote:
>> This patch fixes multiple problems with the current clock calculations:
>>
>> 1. The A10/A20 datasheet contains th
speed instead of tfr->speed_hz for wait time calculation
Marcus Weseloh (3):
spi: dts: Add new device property to specifcy a wait time between word
transmissions
spi: sun4i: Fix clock calculations to be predictable and never exceed
the requested rate
spi: sun4i: Add support for
Modifies the sun4i SPI master driver to make use of the
"spi-word-wait-ns" property. This specific SPI controller needs 3 clock
cycles to set up the delay, which makes the minimum non-zero wait time
on this hardware 4 clock cycles.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com&
Adds a new property "spi-word-wait-ns" to the spi-bus binding that allows
SPI slave devices to set a wait time between the transmission of words.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com>
Reviewed-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Ac
to unpredictable transfer speeds, depending on the order in which
transfers with different speeds where serviced by the SPI driver.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com>
---
drivers/spi/spi-sun4i.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff
Hi,
2015-12-18 12:16 GMT+01:00 Maxime Ripard :
>> sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
>>
>> + /*
>> + * Setup wait time between words.
>> + *
>> + * Wait time is set in SPI_CLK cycles. The SPI hardware needs 3
>> + *
"hardware" in comments and description, as the wait
time could also be implemented in software
* read and set property value in spi core
Changes from v4:
* log with dev_dbg instead of dev_info
* split patch into two separate ones for SPI-core and sun4i parts
Marcus Weseloh (2):
spi:
Adds a new property "spi-word-wait-ns" to the spi-bus binding that allows
SPI slave devices to set a wait time between the transmission of words.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com>
---
Documentation/devicetree/bindings/spi/spi-bus.txt | 2 ++
d
Hi Maxime,
2015-12-16 11:39 GMT+01:00 Maxime Ripard :
> It looks mostly fine, however, please try to make only one thing in
> one patch.
>
> In this case, it would mean having one patch to add the DT property
> and support in the SPI core in a first one, and then
Modifies the sun4i SPI master driver to make use of the
"spi-word-wait-ns" property. This specific SPI controller needs 3 clock
cycles to set up the delay, which makes the minimum non-zero wait time
on this hardware 4 clock cycles.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com&
o make use of the new property.
This specific SPI controller needs 3 clock cycles to set up the delay,
which makes the minimum non-zero wait time on this hardware 4 clock cycles.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com>
---
Changes from v1:
* renamed the property for more clarity
*
2015-12-13 22:07 GMT+01:00 Maxime Ripard :
[...]
>> There is one review comment that I didn't address: Rob Herring suggested
>> that this should be in the core-binding rather than in sun4i. I checked
>> many of the hardware manuals of other SPI drivers and it
to set up the delay, which makes the minimum non-zero wait time
on this hardware 4 clock cycles.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com>
---
Changes from v1:
* renamed the property for more clarity
* wait time is set in nanoseconds instead of number of clock cycles
* transparen
2015-12-14 0:08 GMT+01:00 Mark Brown :
> Please don't bury patches in reply to existing serieses, it makes it
> hard to follow what's going on with regard to which versions are current
> and so on.
Thanks for the pointer, I will send patches like you ask from now on.
Should I
Hi,
2015-12-14 2:29 GMT+01:00 Rob Herring <r...@kernel.org>:
> On Mon, Dec 14, 2015 at 12:04:11AM +0100, Marcus Weseloh wrote:
>> Adds a new property "spi-word-wait-ns" to the spi-bus binding that allows
[...]
>> diff --git a/Documentation/devicetree/bindings/spi/
2015-12-12 10:19 GMT+01:00 Priit Laes <pl...@plaes.org>:
> On Fri, 2015-12-11 at 23:45 +0100, Marcus Weseloh wrote:
> [...]
>> +- sun4i,spi-word-wait-ns: hardware based delay in nanoseconds between
>> + transmission of words
>
> Should be 'allwi
m non-zero wait time 4 clock cycles.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com>
---
Changes from v1:
* renamed the property for more clarity
* wait time is set in nanoseconds instead of number of clock cycles
* transparently handle the 3 setup clock cycles
There is one revie
2015-11-22 20:45 GMT+01:00 Maxime Ripard :
>> Julien, Rob: thanks for your comments! Ok, I will make the following changes:
>>
>> - remove "sun4i,spi-wdelay" from the sun4i binding and add the
>> property to the spi-bus.txt binding instead
>> - remove the comment
Hi Julien,
2015-11-20 11:12 GMT+01:00 Julian Calaby :
> Having magic numbers is kind-of a drivers' job.
Yes, of course. What I meant was that I didn't feel comfortable to
include this magic number in driver code because I'm not 100% sure if
it is correct across all SPI
2015-11-20 17:12 GMT+01:00 Rob Herring <r...@kernel.org>:
> On Fri, Nov 20, 2015 at 02:56:34PM +0100, Marcus Weseloh wrote:
>> > (and the wdelay should
>> > arguably be a core-spi thing, not a sunxi thing, but that's a separate
>> > discussion)
>>
>&
Hi Julian,
2015-11-19 23:59 GMT+01:00 Julian Calaby :
> Should you possibly hide the 3 clock periods from the user?
>
> I.e. they set whatever they want for the wdelay, we set it to the
> closest number we can that's greater or equal to what they ask for.
That's a good
next word.
The constant additional 3 clock periods are not documented by the vendor
and have been determined by analyzing the generated waveforms across
many different transmission speeds.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com>
---
Documentation/devicetree/bindings/spi/sp
umentation. I used "example,dummy" as compatible... is this acceptable or
should I use a device/compatible that actually exists somewhere?
Oh... and should I split binding documentation and code changing patch?
Best regards,
Marcus
Marcus Weseloh (1):
spi: dts: sun4i: Add support
Hi Mark,
2015-11-17 17:57 GMT+01:00 Mark Brown :
>> Just a quick follow-up: is there anything else I need to do to push
>> this patch along? Or do I just need to be more patient?
>
> I don't have this patch, presumably there were review comments that I
> was expecting to see
2015-11-17 19:34 GMT+01:00 Mark Brown :
> Please don't send content free pings and please allow a reasonable time
> for review. People get busy, go on holiday, attend conferences and so
> on so unless there is some reason for urgency (like critical bug fixes)
> please allow at
2015-11-09 4:39 GMT+01:00 Chen-Yu Tsai <w...@csie.org>:
> On Thu, Nov 5, 2015 at 12:51 AM, Marcus Weseloh <mweselo...@gmail.com> wrote:
>> If "Pre-Amplifier DAC" and "Pre-Amplifier Mute" are both off, then
>> aplay hangs for a while and reports "
Allow transfers to set the transmission speed rather than using the
device max_speed_hz value. The SPI core makes sure that the speed_hz
value is always set on the transfer.
Signed-off-by: Marcus Weseloh <mweselo...@gmail.com>
---
Changes from v1:
* Remove fallback to spi->max
Hi Mark,
2015-11-08 10:35 GMT+01:00 Mark Brown <broo...@kernel.org>:
> On Sat, Nov 07, 2015 at 11:41:05PM +0100, Marcus Weseloh wrote:
>
>> + /* Transfer speed setup with fallback to board max_speed_hz */
>> + if (tfr->speed_hz > 0 &&a
2015-11-08 11:13 GMT+01:00 Marcus Weseloh <mweselo...@gmail.com>:
> I did notice however, that the SPI system doesn't validate the
> speed_hz value. So if I leave out the above quoted sanity checking,
> then tfr->speed_hz could also contain values like -400, which trips u
Hi all,
first of all: thank you very much for all your work on mainlining the
Allwinner chips, especially for adding OTG and audio codec support!
I've been testing the audio codec using the linux-sunxi/sunxi-next
branch on my Olimex SOM EVB. It works great, but it took me a while to
find the
the two initialisation statements before the function call.
Signed-off-by: Marcus Weseloh mar...@weseloh.cc
---
drivers/usb/gadget/f_midi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/f_midi.c b/drivers/usb/gadget/f_midi.c
index 1bf9596..1c16bcb 100644
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