ver, he didn't add
> a Signed-off-by tag here to his commit. So I take this code and added my
> Signed-off-by.
Well, here it is if that helps:
Signed-off-by: Ondřej Jirman
Though this might be somewhat difficult change to make. It works
perfectly when combined with kernel that will not
Hi Maxime,
Maxime Ripard píše v Po 10. 04. 2017 v 08:59 +0200:
> On Mon, Apr 10, 2017 at 12:19:41AM +0800, Icenowy Zheng wrote:
> > According to the researching result of Ondrej Jirman, the factor M of
> > PLL1 shouldn't be used and the factor P should be used only if the
> > intended frequency is
Hi Icenowy,
I already tried this approach to changing CPUX_PLL and it didn't work
well. I've written a test program for CPUS (additional RISC-V processor
on H3 SoC) for testing various NKMP clock change algorithms, by
randomly changing the PLL frequency. Everything except simply not using
dividers
Hi,
Dne 14.3.2017 v 07:53 Jernej Škrabec napsal(a):
> Hi,
>
> Dne ponedeljek, 13. marec 2017 ob 13:33:43 CET je Simon Glass napisal(a):
>> Hi,
>>
>> On 8 March 2017 at 16:34, Jernej Skrabec wrote:
>>> This is needed for HDMI, which will be added later.
>>>
>>> Signed-off-by: Jernej Skrabec
>>>
Hi Icenowy,
when I was trying to add OTG support I found an issue with powercycling.
When I have USB cable connecting PC and the OTG port on the SBC, when
the board enables the vbus, it would become impossible to power cycle
the board after poweroff. The reason being that when vbus is enabled,
the
Dne 18.1.2017 v 17:56 Maxime Ripard napsal(a):
>>> What's your current plan to fix that? I guess the easiest (and most
>>> likely to be reusable) would be to allow for clock tables, instead of
>>> using the generic approach. We might have some other clocks (like
>>> audio or video) that would need
Dne 16.1.2017 v 20:14 Icenowy Zheng napsal(a):
> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> controller.
>
> The original driver wired it to OHCI/EHCI controller; however, as the
> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
> unusable.
>
> Rename the
Hi Maxime,
Dne 16.1.2017 v 17:43 Maxime Ripard napsal(a):
>> It does lock up quickly with mainline ccu_nkmp_find_best algorithm
>> for finding factors.
>>
>> Even with linux kernel, it breaks. It's just more difficult to hit the
>> right conditions. I got oops only right after boot when running cp
Dne 9.1.2017 v 10:59 Maxime Ripard napsal(a):
> On Sat, Jan 07, 2017 at 04:49:18PM +0100, Ondřej Jirman wrote:
>> Maxime,
>>
>> Dne 25.11.2016 v 01:28 meg...@megous.com napsal(a):
>>> From: Ondrej Jirman
>>>
>>> When adjusting PLL_CPUX on H3, the
Maxime,
Dne 25.11.2016 v 01:28 meg...@megous.com napsal(a):
> From: Ondrej Jirman
>
> When adjusting PLL_CPUX on H3, the PLL is temporarily driven
> too high, and the system becomes unstable (oopses or hangs).
>
> Add a notifier to avoid this situation by temporarily switching
> to a known stab
Dne 25.11.2016 v 06:27 Icenowy Zheng napsal(a):
>
>
> 20.11.2016, 20:07, "Jean-Francois Moine" :
>> Signed-off-by: Jean-Francois Moine
>> ---
>> arch/arm/boot/dts/sun8i-h3.dtsi | 51
>> +
>> 1 file changed, 51 insertions(+)
>>
>> diff --git a/arch/arm/bo
Dne 21.11.2016 v 19:14 Jean-Francois Moine napsal(a):
> On Mon, 21 Nov 2016 01:54:53 +0100
> Ondřej Jirman wrote:
>
>> Dne 20.11.2016 v 12:32 Jean-Francois Moine napsal(a):
>>> This patchset series adds HDMI video support to the Allwinner
>>> sun8i SoCs which
Dne 20.11.2016 v 12:32 Jean-Francois Moine napsal(a):
> This patchset series adds HDMI video support to the Allwinner
> sun8i SoCs which include the display engine 2 (DE2).
> The driver contains the code for the A83T and H3, but it could be
> used/extended for other SoCs as the A64, H2 and H5.
Hi,
Dne 1.11.2016 v 00:55 Rune Petersen napsal(a):
> On 25/10/16 16:36, Olliver Schinagl wrote:
>> Hey all,
>>
>> as some of you are probably aware, some users occasionally experience
>> some
>> instability using the mainline components. I specifically only want to
>> focus on
>> mainline, as with the
Dne 24.10.2016 v 05:59 Icenowy Zheng napsal(a):
> Allwinner SoC's PHY 0, when used as OTG controller, have no pmu part.
> The code that poke some unknown bit of PMU for H3/A64 didn't check
> the PHY, and will cause kernel oops when PHY 0 is used.
>
> Fixes: b3e0d141ca9f (phy: sun4i: add support fo
Dne 22.10.2016 v 15:28 Jean-Francois Moine napsal(a):
> This patchset series adds HDMI audio and video support to the Allwinner
> sun8i SoCs which include the display engine 2 (DE2).
Hi,
I've tested your patches on top of my 4.9-rc1 changes on Orange Pi PC,
and HDMI display output works well -- w
Hi,
I think you may be hitting this issue:
https://lkml.org/lkml/2016/8/26/150
regards,
Ondrej
Dne 27.8.2016 v 00:07 Paulo Costa napsal(a):
> Hello, folks.
>
> It's my first time working with this, please let me know if this isn't
> the right mailing list or not the right way to ask for he
Hi,
On 31.7.2016 12:31, Maxime Ripard wrote:
> Hi,
>
> On Fri, Jul 29, 2016 at 12:01:09AM +0200, Ondřej Jirman wrote:
>> On 28.7.2016 23:00, Maxime Ripard wrote:
>>> Hi Ondrej,
>>>
>>> On Thu, Jul 28, 2016 at 01:27:05PM +0200, Ondřej Jirman wrote:
&
On 28.7.2016 23:00, Maxime Ripard wrote:
> Hi Ondrej,
>
> On Thu, Jul 28, 2016 at 01:27:05PM +0200, Ondřej Jirman wrote:
>> Hi Maxime,
>>
>> I don't have your sunxi-ng clock patches in my mailbox, so I'm replying
>> to this.
>
> You c
Hi Maxime,
I don't have your sunxi-ng clock patches in my mailbox, so I'm replying
to this.
On 26.7.2016 08:32, Maxime Ripard wrote:
> On Thu, Jul 21, 2016 at 11:52:15AM +0200, Ondřej Jirman wrote:
>>>>> If so, then yes, trying to switch to the 24MHz oscillator befor
On 26.7.2016 08:32, Maxime Ripard wrote:
> On Thu, Jul 21, 2016 at 11:52:15AM +0200, Ondřej Jirman wrote:
>>>>> If so, then yes, trying to switch to the 24MHz oscillator before
>>>>> applying the factors, and then switching back when the PLL is stable
>>>
Hello Michal,
On 30.6.2016 13:13, Michal Suchanek wrote:
> Hello,
>
> On 25 June 2016 at 05:45, wrote:
>> From: Ondrej Jirman
>>
>> Use Xulong Orange Pi One GPIO based regulator for
>> passive cooling and thermal management.
>>
>> Signed-off-by: Ondrej Jirman
>> ---
>> arch/arm/boot/dts/sun8
On 21.7.2016 11:48, Maxime Ripard wrote:
> On Fri, Jul 15, 2016 at 12:38:54PM +0200, Ondřej Jirman wrote:
>> On 15.7.2016 10:53, Maxime Ripard wrote:
>>> On Fri, Jul 01, 2016 at 02:50:57AM +0200, Ondřej Jirman wrote:
>>>>>> /**
>>>>>>
On 25.6.2016 09:02, Maxime Ripard wrote:
> On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
>> On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman wrote:
>>> Hello,
>>>
>>> comments below.
>>>
>>> On 24.6.2016 05:48, Chen-Yu Tsa
On 15.7.2016 16:22, Michal Suchanek wrote:
> Hello,
>
> On 15 July 2016 at 15:48, Ondřej Jirman wrote:
>>
>>
>> On 15.7.2016 15:27, Jean-Francois Moine wrote:
>>> On Fri, 15 Jul 2016 12:38:54 +0200
>>> Ondřej Jirman wrote:
>>>
>>&
On 15.7.2016 15:27, Jean-Francois Moine wrote:
> On Fri, 15 Jul 2016 12:38:54 +0200
> Ondřej Jirman wrote:
>
>>> If so, then yes, trying to switch to the 24MHz oscillator before
>>> applying the factors, and then switching back when the PLL is stable
>>>
On 15.7.2016 10:53, Maxime Ripard wrote:
> On Fri, Jul 01, 2016 at 02:50:57AM +0200, Ondřej Jirman wrote:
>>>> /**
>>>> + * sun8i_h3_apply_pll1_factors() - applies n, k, m, p factors to the
>>>> + * register using an algorithm that tries to reserve the PLL
On 1.7.2016 13:19, Michal Suchanek wrote:
> On 1 July 2016 at 13:02, Michal Suchanek wrote:
>> On 30 June 2016 at 22:30, Ondřej Jirman wrote:
>>> On 30.6.2016 20:21, Michal Suchanek wrote:
>>>> On 30 June 2016 at 20:06, Michal Suchanek wrote:
>>>>>
On 1.7.2016 07:37, Jean-Francois Moine wrote:
> On Fri, 1 Jul 2016 02:50:57 +0200
> Ondřej Jirman wrote:
>
>>> Since this is really specific, I guess you could simply make the
>>> clk_ops for the nkmp clocks public, and just re-implement set_rate
>>> using
On 30.6.2016 16:23, Siarhei Siamashka wrote:
> On Thu, 30 Jun 2016 13:13:48 +0200
> Michal Suchanek wrote:
>
>> Hello,
>>
>> On 25 June 2016 at 05:45, wrote:
>>> From: Ondrej Jirman
>>>
>>> Use Xulong Orange Pi One GPIO based regulator for
>>> passive cooling and thermal management.
>>>
>>> S
On 30.6.2016 22:40, Maxime Ripard wrote:
> Hi,
>
> On Sat, Jun 25, 2016 at 05:45:03AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman
>>
>> PLL1 on H3 requires special factors application algorithm,
>> when the rate is changed. This algorithm was extracted
>> from the arisc code that handl
Hi,
On 30.6.2016 22:40, Maxime Ripard wrote:
> Hi,
>
> On Sat, Jun 25, 2016 at 05:45:03AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman
>>
>> PLL1 on H3 requires special factors application algorithm,
>> when the rate is changed. This algorithm was extracted
>> from the arisc code that
On 30.6.2016 20:21, Michal Suchanek wrote:
> On 30 June 2016 at 20:06, Michal Suchanek wrote:
>> Hello,
>>
>> On 30 June 2016 at 16:44, Ondřej Jirman wrote:
>>> Hi,
>>>
>>> hopefuly, it was the NPE that I fixed. It was specifically in the H3 usb
On 30.6.2016 17:50, Michal Suchanek wrote:
> On 30 June 2016 at 17:16, Michal Suchanek wrote:
>> On 30 June 2016 at 16:19, Ondřej Jirman wrote:
>>> Hello,
>>>
>>> On 30.6.2016 13:13, Michal Suchanek wrote:
>>>> Hello,
>>>>
>&
On 30.6.2016 17:16, Michal Suchanek wrote:
> On 30 June 2016 at 16:19, Ondřej Jirman wrote:
>> Hello,
>>
>> On 30.6.2016 13:13, Michal Suchanek wrote:
>>> Hello,
>>>
>>> On 25 June 2016 at 05:45, wrote:
>>>> From: Ondrej Jirman
Hi,
hopefuly, it was the NPE that I fixed. It was specifically in the H3 usb
phy code path for phy0. So I believe it was untested,
because I didn't find any dts file that would use phy0.
Good luck with the audio driver.
regards,
o.
On 30.6.2016 07:17, boob...@gmail.com wrote:
> Nice work.
>
Hello,
On 30.6.2016 13:13, Michal Suchanek wrote:
> Hello,
>
> On 25 June 2016 at 05:45, wrote:
>> From: Ondrej Jirman
>>
>> Use Xulong Orange Pi One GPIO based regulator for
>> passive cooling and thermal management.
>>
>> Signed-off-by: Ondrej Jirman
>> ---
>> arch/arm/boot/dts/sun8i-h3-or
On 29.6.2016 22:45, Maxime Ripard wrote:
> Hi,
>
> On Sat, Jun 25, 2016 at 04:50:24PM +0200, Ondřej Jirman wrote:
>> On 25.6.2016 09:02, Maxime Ripard wrote:
>>> On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
>>>> On Sat, Jun 25, 2016 at 6:51 A
On 28.6.2016 17:37, Jean-Francois Moine wrote:
> Most of the clocks in the Allwinner's SoCs are configured in the CCU
> (Clock Configuration Unit).
>
> The PLL clocks are driven from the main clock. Their rates are controlled
> by a set of multiply and divide factors, named from the Allwinner's
>
Hi,
if anyone wants to play with the OTG port support on Orange Pi PC, you
can try these patches:
https://files.megous.com/orange-pi-dvfs/linux-4.7-OrangePI/usb-otg/
I don't have much time to test it extensively, but it seems to work.
I'm not yet submitting them "formally". This is just a heads
On 27.6.2016 16:54, Mark Brown wrote:
> On Sun, Jun 26, 2016 at 05:07:16PM +0200, Ondřej Jirman wrote:
>> On 26.6.2016 13:26, Mark Brown wrote:
>
>>> I'm missing almost all of this series, I've just got this and another
>>> patch which look like a s
On 26.6.2016 13:27, Mark Brown wrote:
> On Sat, Jun 25, 2016 at 05:45:02AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman
>>
>> This patch adds the binding documentation for the
>> sy8106a regulator driver.
>
> Please submit patches using subject lines reflecting the style for the
> subsy
On 26.6.2016 13:26, Mark Brown wrote:
> On Sat, Jun 25, 2016 at 05:45:01AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman
>>
>> SY8106A is I2C attached single output voltage regulator
>> made by Silergy.
>
> I'm missing almost all of this series, I've just got this and another
> patch whi
Hi Maxime,
I try to base everything on the torvalds's kernel.
I did notice the patches. Is there some main git tree/branch where this
work is tracked in? I'd gladly use it.
Also there's a PLL1 rate application patch, that would need to be ported
to the new CCU code, in the case I would use it as
On 25.6.2016 09:10, Maxime Ripard wrote:
> On Sat, Jun 25, 2016 at 05:44:59AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman
>>
>> This patch adds support for the sun8i thermal sensor on
>> Allwinner H3 SoC.
>>
>> Signed-off-by: Ondřej Jirman
>
On 25.6.2016 09:02, Maxime Ripard wrote:
> On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
>> On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman wrote:
>>> Hello,
>>>
>>> comments below.
>>>
>>> On 24.6.2016 05:48, Chen-Yu Tsa
On 25.6.2016 02:54, Chen-Yu Tsai wrote:
> On Sat, Jun 25, 2016 at 8:35 AM, Ondřej Jirman wrote:
>> On 24.6.2016 05:09, Chen-Yu Tsai wrote:
>>>> +static int sun8i_ths_h3_init(struct platform_device *pdev,
>>>> +struct sun8i_ths_data *d
On 24.6.2016 05:09, Chen-Yu Tsai wrote:
>> +static int sun8i_ths_h3_init(struct platform_device *pdev,
>> +struct sun8i_ths_data *data)
>> +{
>> + int ret;
>> + size_t callen;
>> + s32 *caldata;
>> +
>> + data->busclk = devm_clk_get(&pdev->dev, "a
_REGULATOR_SY8106A) += sy8106a-regulator.o
>
> Follow the existing ordering in the Makefile.
>
>>
>> ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
>> diff --git a/drivers/regulator/sy8106a-regulator.c
>> b/drivers/regulator/sy8106a-regulator.c
>> new file m
Hello,
comments below.
On 24.6.2016 05:48, Chen-Yu Tsai wrote:
> On Fri, Jun 24, 2016 at 3:20 AM, wrote:
>> From: Ondrej Jirman
>>
>> Add label to the first cpu so that it can be referenced
>> from derived dts files.
>>
>> Signed-off-by: Ondrej Jirman
>> ---
>> arch/arm/boot/dts/sun8i-h3.dts
Hi Julian,
thank you for the review. You're right. I added the pinctrl client
nodes. Also the patches were split incorrectly, so I fixed that too.
regards,
Ondrej
On 24.6.2016 04:51, Julian Calaby wrote:
> Hi Ondrej,
>
> On Fri, Jun 24, 2016 at 5:21 AM, wrote:
>> From: Ondrej Jirman
>>
>>
gt;
> The subject could read:
>
> thermal: sun8i_ths: Add support for the thermal sensor on Allwinner H3
>
>> This patch adds support for the sun8i thermal sensor on
>> Allwinner H3 SoC.
>>
>> Signed-off-by: Ondřej Jirman
>> ---
>> drivers/thermal/Kco
Hello,
thank you for the review.
On 24.6.2016 04:41, Chen-Yu Tsai wrote:
> On Fri, Jun 24, 2016 at 3:20 AM, wrote:
>> From: Josef Gajdusek
>>
>> Add a node describing the Security ID memory to the Allwinner H3 .dtsi file.
>>
>> Signed-off-by: Josef Gajdusek
>> ---
>> arch/arm/boot/dts/sun8i-
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