Re: [linux-sunxi] [PATCH v4 1/8] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

2017-03-20 Thread Chen-Yu Tsai
On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote: > Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two > controllers: one is MUSB and the other is a EHCI/OHCI pair. > > When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to > tweak, like

[linux-sunxi] [PATCH v4 1/8] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

2017-03-19 Thread Icenowy Zheng
Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allwinner SoCs. Add this to the binding of USB PHYs on