Dear Ian,
On Sun, 2014-04-27 at 19:47 +0100, Ian Campbell wrote:
This is the driver for one particular ARM cache controller and not the
one used for the SoC. In any case it does proper start/end handling
only for cache flush operations, not cache invalidate.
Cache invalidate is a
CCing the ARM custodian. Albert, what do you think of Alexey's comments
below? Actually, having read it properly myself I think Alexey is
confusing cache flushing with cache invalidation, I've left the CC in
place though in case you have any thoughts on the matter.
On Fri, 2014-04-25 at 08:48
Hi Ian,
On Thu, 2014-04-24 at 20:14 +0100, Ian Campbell wrote:
On Thu, 2014-04-24 at 17:41 +, Alexey Brodkin wrote:
1. Don't invalidate sizeof(struct dmamacdescr) but only
roundup(sizeof(desc_p-txrx_status), ARCH_DMA_MINALIGN)).
OK. (Although given the realities of the real world
Dear Ian,
On Sat, 2014-04-19 at 14:52 +0100, Ian Campbell wrote:
- /* Invalidate only status field for the following check */
- invalidate_dcache_range((unsigned long)desc_p-txrx_status,
- (unsigned long)desc_p-txrx_status +
-
On Sat, 2014-04-19 at 10:14 -0400, Stefan Monnier wrote:
Some platforms cannot invalidate the cache at four byte intervals, so
invalidate the entire descriptor.
Wouldn't it be simpler to make invalidate_dcache_range round up to the
nearest aligned boundaries?
Can there ever be
invalidate here means throw away the content of the cache line
Duh! Sorry for the noise!
Stefan
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