[linux-sunxi] Re: [PATCH v2 06/26] clk: sunxi: Add PLL3 clock

On Sun, Jan 17, 2016 at 12:05:06AM +0800, Chen-Yu Tsai wrote: > Hi, > > On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard > wrote: > > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > > PLL7, clocked from a 3MHz oscillator, that drives the

[linux-sunxi] Re: [PATCH v2 06/26] clk: sunxi: Add PLL3 clock

Hi, On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard wrote: > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > PLL7, clocked from a 3MHz oscillator, that drives the display related > clocks (GPU, display engine, TCON, etc.) > > Add a

[linux-sunxi] Re: [PATCH v2 06/26] clk: sunxi: Add PLL3 clock

On Thu, Jan 14, 2016 at 04:24:49PM +0100, Maxime Ripard wrote: > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > PLL7, clocked from a 3MHz oscillator, that drives the display related > clocks (GPU, display engine, TCON, etc.) > > Add a driver for it. > > Signed-off-by: