On Fri, 2014-07-25 at 03:21 +0300, Siarhei Siamashka wrote:
On Mon, 21 Jul 2014 21:59:51 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-07-21 at 22:39 +0200, Jeroen Hofstee wrote:
Hello Ian,
On 21-07-14 22:07, Ian Campbell wrote:
On Fri, 2014-07-18 at 20:47 +0200,
On Mon, 21 Jul 2014 21:59:51 +0100
Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-07-21 at 22:39 +0200, Jeroen Hofstee wrote:
Hello Ian,
On 21-07-14 22:07, Ian Campbell wrote:
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote:
Hello Siarhei,
On 18-07-14 19:09,
On Sat, 2014-07-19 at 13:20 +0200, Hans de Goede wrote:
Hi,
On 07/18/2014 07:09 PM, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is set
by the BROM code right from the start.
If
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote:
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is set
by the BROM code right from the start.
On Mon, 2014-07-21 at 19:39 +0100, Ian Campbell wrote:
I expect this needs to be done on secondary processors. Need to keep
that in mind if/when someone works on PSCI for sun[45]i.
Except as Tom points out on IRC, sun[45]i are both single core... Oops!
Ian.
--
You received this message
On Mon, 2014-07-21 at 22:39 +0200, Jeroen Hofstee wrote:
Hello Ian,
On 21-07-14 22:07, Ian Campbell wrote:
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote:
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot
Hello Ian,
On 21-07-14 22:07, Ian Campbell wrote:
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote:
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is
Hi,
On 07/18/2014 07:09 PM, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is set
by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is set
by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2
