24.03.2017, 14:56, "Chen-Yu Tsai" :
> On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng wrote:
>> 24.03.2017, 11:05, "Chen-Yu Tsai" :
>>> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
register offset missin
On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng wrote:
>
>
> 24.03.2017, 11:05, "Chen-Yu Tsai" :
>> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
>>> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>>> register offset missing.
>>>
>>> Add it. Because it's a SoC after
24.03.2017, 11:05, "Chen-Yu Tsai" :
> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
>> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>> register offset missing.
>>
>> Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
>
> You are implying tha
On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
> register offset missing.
>
> Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
You are implying that all SoCs after A33 have PHYCTL at 0x10.
This is