Hi All,
After a bit of a pause due to -ENOTIME, here is my 2nd attempt at getting
support for the lradc attached tablet keys found one some Allwinner boards
upstream.
I've dubbed this v2 even though there has been more then one version before
because I've lost count, and as said this represents
On Tue, 2014-10-21 at 02:28 +0300, Vladimir Zapolskiy wrote:
On 19.10.2014 17:16, LABBE Corentin wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
[]
Add driver for the power supply features of AXP20x PMIC.
Covered features:
- backup / RTC battery
- VBUS/OTG power input
- AC power input
- LIon battery charger
---
drivers/mfd/axp20x.c | 106 +-
drivers/power/Kconfig|9 +
Hello LABBE,
On 19.10.2014 17:16, LABBE Corentin wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 48 +
arch/arm/boot/dts/sun7i-a20.dtsi| 7
2 files changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
This series adds a power-supply driver to cover backup/RTC battery
charger, VBUS/OTG power in, AC power in and battery charger features
supported by AXP20x PMIC.
The DT bindings documentation patch depends on the following patch
from Carlo Caione:
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts |4 +
1 files changed, 2 insertions(+), 0 deletion(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index a6c1a3c..efb65fb 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++
On Mon, 20 Oct 2014, Bruno Prémont wrote:
---
Note: the OCV values seem to have some defaults build into the
PMIC though may need adjustment if the used battery has a different
open circuit voltage curve.
As far as understood (these values are set in vendor driver but not
mentioned in
I checked the connections... But no short connection between any four
points. I just connected X1,X2,Y1,Y2 directly to the pins of A20 board as
described. Does it need any resistor,capacitor in the connection..??? What
about sunxi-ts.c ??? Is it in proper working condition??? It is found in
Hi Brian,
On Mon, 20 Oct 2014 19:41:34 -0700
Brian Norris computersforpe...@gmail.com wrote:
Hi Boris,
On Mon, Oct 20, 2014 at 01:45:20PM +0200, Boris Brezillon wrote:
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris Brezillon
OK vi agora V7 vou testar
Em terça-feira, 21 de outubro de 2014 11h13min16s UTC-2, Ezaul Zillmer
escreveu:
Hello everyone
Boris Brezillon
downloaded sunxi-nand-v6 now compiled for Cubieboard2
https://github.com/bbrezillon/linux-sunxi.git sunxi b-nand-v6
u-boot
git clone
On Tue, 21 Oct 2014 06:13:16 -0700 (PDT)
Ezaul Zillmer ezaulzill...@gmail.com wrote:
Hello everyone
Boris Brezillon
downloaded sunxi-nand-v6 now compiled for Cubieboard2
https://github.com/bbrezillon/linux-sunxi.git sunxi b-nand-v6
u-boot
git clone
On 10/21/14 01:28, Vladimir Zapolskiy wrote:
Hello LABBE,
On 19.10.2014 17:16, LABBE Corentin wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
[]
+
+
Hi Hans,
Thanks, a lot for respinning this.
On Tue, Oct 21, 2014 at 10:24:47AM +0200, Hans de Goede wrote:
Allwinnner sunxi SoCs have a low resolution adc (called lradc) which is
specifically designed to have various (tablet) keys (ie home, back, search,
etc). attached to it using a resistor
Hi Corentin,
On 21.10.2014 19:25, Corentin LABBE wrote:
On 10/21/14 01:28, Vladimir Zapolskiy wrote:
Hello LABBE,
On 19.10.2014 17:16, LABBE Corentin wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that
On Fri, 2014-10-17 at 22:48 +0800, Chen-Yu Tsai wrote:
Hi Ian,
On Mon, Oct 13, 2014 at 8:57 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, Oct 12, 2014 at 04:23:05PM +0800, Chen-Yu Tsai wrote:
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell i...@hellion.org.uk wrote:
On Sun, 2014-10-12 at 22:17 +0100, Ian Campbell wrote:
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
+ default sun4i if TARGET_SUN4I
+ default sun5i if TARGET_SUN5I
+ default sun6i if TARGET_SUN5I
There is a typo here which is apparent with MAKEALL -s sunxi, since
Hi Corentin,
Thanks for resending it.
On Sun, Oct 19, 2014 at 04:16:22PM +0200, LABBE Corentin wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Hi Bruno,
Thanks a lot for working on this!
On Tue, Oct 21, 2014 at 06:09:16PM +0200, Bruno Prémont wrote:
On Tue, 21 October 2014 Lee Jones lee.jo...@linaro.org wrote:
On Mon, 20 Oct 2014, Bruno Prémont wrote:
---
Note: the OCV values seem to have some defaults build into the
PMIC
On Tue, Oct 21, 2014 at 08:03:59PM +0100, Ian Campbell wrote:
On Sun, 2014-10-12 at 22:17 +0100, Ian Campbell wrote:
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
+ default sun4i if TARGET_SUN4I
+ default sun5i if TARGET_SUN5I
+ default sun6i if TARGET_SUN5I
On Mon, Oct 20, 2014 at 10:10:26PM +0800, Chen-Yu Tsai wrote:
Some of the factors-style clocks on the A80 have different widths
for the mux values in the registers.
Add a .muxmask field to clk_factors_config to make it configurable.
Passing a bitmask instead of a width parameter will allow
On Mon, Oct 20, 2014 at 10:10:27PM +0800, Chen-Yu Tsai wrote:
The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new GT bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.
As
On Mon, Oct 20, 2014 at 10:10:28PM +0800, Chen-Yu Tsai wrote:
This adds the gate clocks for AHB/APB busses on the A80 SoC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
On Mon, Oct 20, 2014 at 10:10:30PM +0800, Chen-Yu Tsai wrote:
Now that we have driver support for the basic clocks, add them to the
dtsi and update existing peripherals. Also add reset controls to match.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Applied, thanks!
Maxime
--
Maxime Ripard,
24 matches
Mail list logo