On Wed, May 06, 2015 at 12:18:11PM +0200, Jens Kuske wrote:
/**
* sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
*
@@ -1252,6 +1288,7 @@ static const struct of_device_id clk_factors_match[]
__initconst = {
{.compatible = allwinner,sun5i-a13-ahb-clk,
On Wed, May 06, 2015 at 11:31:29AM +0200, Jens Kuske wrote:
The H3 clock control unit is similar to the those of other sun8i family
members like the A23.
The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
being muxable between AHB1 and PLL6/2, but still sharing gate
On Wed, May 06, 2015 at 10:47:33PM +0200, Jens Kuske wrote:
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
hi,all,
how to get a20 encoder output frameType?
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Hi,
On 07/05/15 10:10, Paul Bolle wrote:
On Wed, 2015-05-06 at 11:31 +0200, Jens Kuske wrote:
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
+config PINCTRL_SUN8I_H3
+def_bool MACH_SUN8I
+select PINCTRL_SUNXI_COMMON
--- a/drivers/pinctrl/sunxi/Makefile
On Sat, May 09, 2015 at 11:17:51AM +0200, Jens Kuske wrote:
+MODULE_DEVICE_TABLE(of, sun8i_h3_pinctrl_match);
+MODULE_AUTHOR(Jens Kuske jensku...@gmail.com);
+MODULE_DESCRIPTION(Allwinner H3 pinctrl driver);
+MODULE_LICENSE(GPL);
This adds some module specific boilerplate. Was it
Hi,
On 06-05-15 11:31, Jens Kuske wrote:
Hi everyone,
This patch series introduces basic kernel support for Allwinner's H3 SoC,
mainly basic clocks and pinctrl. It also adds interrupts, timers,
watchdog, RTC, dmaengine, MMC and UARTs, which are mostly compatible to
those in earlier SoCs like
On Friday, May 8, 2015 at 12:31:52 PM UTC+3, stu...@gmail.com wrote:
Dear All;
I would like to enable SIR mode in UART modem control register for only one
of my UART ports. I am planning to transceive IrDa by using that port.
In A20 User manual, page 655, it states that 6th bit of
