Enable the WiFi (AP6212) chip and eMMC support for the NanoPi NEO Air.
Signed-off-by: Jelle van der Waa
---
arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts | 45 +++
1 file changed, 45 insertions(+)
diff --git
Enable the WiFi (AP6212) chip and eMMC support for the NanoPi NEO Air.
---
Fixes in v2:
- Rename underscore nodes
- Remove allwinner prefix from GPIO node and use generic properties
Jelle van der Waa (1):
ARM: dts: sun8i: NanoPi NEO Air add WiFi / eMMC
Hi,
On Wed, Mar 22, 2017 at 12:34:45PM +0800, Chen-Yu Tsai wrote:
> P.S. I'm thinking about having MFD_AXP20X imply its various sub-drivers.
> Not sure if that was the intended usage of the new imply syntax though.
I think adding "default MFD_AXP20X" to the sub-drivers is cleaner,
as you will
On Thu, Mar 23, 2017 at 5:35 PM, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Mar 22, 2017 at 12:34:45PM +0800, Chen-Yu Tsai wrote:
>> P.S. I'm thinking about having MFD_AXP20X imply its various sub-drivers.
>> Not sure if that was the intended usage of the new imply syntax though.
Yes my mainline u-boot do display , boot log and tux , but i replaced that
with a full screen bmp :) , my problem is the mainline kernel boot log
(console) is not graphical like the old 3.4 , and doesnt show a TUX , and
plymouth doesnt work , i'm on A23 Q8 Tablet
On Thursday, March 23, 2017 at
On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
> register offset missing.
>
> Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
You are implying that all SoCs after A33 have
On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
> It seems that all SoCs after A33 (including A33) need the PHYCTL
> register to be cleared before writing to it. These SoCs all have another
> feature: PHYCTL register is at 0x10, not 0x04.
As mentioned in the other patch,
On Mon, Mar 20, 2017 at 12:31 AM, Icenowy Zheng wrote:
> Orange Pi Zero board features a USB OTG port, which has a ID pin, and
> can be used to power up the board. However, even if the board is powered
> via +5V pin in GPIO/expansion headers, the VBUS in the OTG port cannot
> be
On Mon, Mar 20, 2017 at 12:31 AM, Icenowy Zheng wrote:
> Orange Pi PC 2 board features a OTG port like the one on older H3 Orange
> Pi's, with PG12 pin being the id det pin and PL2 being the vbus driver
> pin.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
On Tuesday, March 21, 2017 at 4:06:56 PM UTC+1, Petar Dimitrijevic wrote:
>
> Hi,
>
> I've received a V3s development board few days ago. It has an android FW
> with Camdroid installed booting from SPI NOR flash.
> Picture of the board as well as the fex file are attached to this message.
>
>
>
On Thu, Mar 23, 2017 at 1:00 PM, Petar Dimitrijevic
wrote:
> Thank you very much for IRC contact. I will definitely contact you there.
>
> One more question. I've turned on debugging in uboot. And here is what I
> get:
>
>> U-Boot SPL
Thank you very much for IRC contact. I will definitely contact you there.
One more question. I've turned on debugging in uboot. And here is what I
get:
U-Boot SPL 2017.01-rc2-01115-g252ef38050-dirty (Mar 23 2017 - 17:50:16)
> DRAM: 64 MiB
> >>spl:board_init_r()
> Trying to boot from MMC1
> init
On Thu, Mar 23, 2017 at 2:00 PM, Petar Dimitrijevic
wrote:
>
>
> On Tuesday, March 21, 2017 at 4:06:56 PM UTC+1, Petar Dimitrijevic wrote:
>>
>> Hi,
>>
>> I've received a V3s development board few days ago. It has an android FW
>> with Camdroid installed booting from
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