Re: [linux-sunxi] [PATCH v3 03/12] ASoC: sun4i-i2s: Add regmap config to quirks

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > The newer SoCs have a larger range than the original SoC that this > driver was developed for. By adding the regmap config to the quirks > then the driver can initialise the managed

Re: [linux-sunxi] [PATCH v3 04/12] ASoC: sun4i-i2s: Add TX FIFO offset to quirks

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > It has been seen that the newer SoCs have a different TX FIFO > address. Add this to the quirks structure. > > Signed-off-by: Marcus Cooper Reviewed-by: Chen-Yu

Re: [linux-sunxi] [PATCH v3 05/12] ASoC: sun4i-i2s: Add regmap fields for channels

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > On the original i2s block the channel mapping and selection were > configured for stereo audio by default: This is not the case with > the newer SoCs and they are also located at

Re: [linux-sunxi] [PATCH v3 06/12] ASoC: sun4i-i2s: Add changes for wss and sr

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > On newer SoCs the location of the slot width select and sample > resolution are different and also there is a bigger range of > support. There is enough space to not use acronyms in

Re: [linux-sunxi] [PATCH v3 07/12] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > On newer SoCs the bit fields for the blck and lrclk polarity are in > a different locations. Use regmap fields to set the polarity bits > as intended. > > Signed-off-by: Marcus Cooper

Re: [linux-sunxi] [PATCH 00/13] Allwinner H3 DE2 basical support

On Tue, Aug 1, 2017 at 9:12 PM, Icenowy Zheng wrote: > Allwinner H3 features a "Display Engine 2.0", which needs some support > to be present in the DRM driver. > > This patchset is now a basical version, which dropped some features I > used to submitted: > - TVE support (not so

Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

在 2017-08-02 12:53，Jernej Škrabec 写道： Hi Icenowy, Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng napisal(a): Allwinner H3 features a "Display Engine 2.0". Add device tree bindings for the following parts: - H3 TCONs - H3 Mixers - H3 Display engine Signed-off-by: Icenowy Zheng

Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

在 2017-08-02 12:47，Jernej Škrabec 写道： Hi Icenowy, Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a): As we have already the support for the DE2 on Allwinner H3, add the display engine pipeline device tree nodes to its DTSI file. The H5 pipeline has some differences and

Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

Hi Icenowy, Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a): > As we have already the support for the DE2 on Allwinner H3, add the > display engine pipeline device tree nodes to its DTSI file. > > The H5 pipeline has some differences and will be enabled later. > >

Re: [linux-sunxi] [PATCH v3 09/12] ASoC: sun4i-i2s: Add regmap field to set format

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > On the newer SoCs the bits to configure the operational mode are The subject says "format". Which is it? And please be clear what "mode" or "format" this configures. Is it the DAI

Re: [linux-sunxi] [PATCH v3 11/12] ASoC: sun4i-i2s: Update global enable with bitmask

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > The default value of the config register is different on newer > SoCs and therefore enabling/disabling with a register write > will clear bits used to set the direction of the clock

Re: [linux-sunxi] [PATCH v3 06/12] ASoC: sun4i-i2s: Add changes for wss and sr

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > On newer SoCs the location of the slot width select and sample > resolution are different and also there is a bigger range of > support. > > For the current supported rates then an

Re: [linux-sunxi] [PATCH v3 10/12] ASoC: sun4i-i2s: Check for slave select bit

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > The newer SoCs do not have this setting. Instead they set the pin > direction. Add a check to see if the bit is valid and if so set > it accordingly. > > Signed-off-by: Marcus Cooper

Re: [linux-sunxi] [PATCH v3 12/12] ASoC: sun4i-i2s: Add support for H3

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > The sun8i-h3 introduces a lot of changes to the i2s block such > as different register locations, extended clock division and > more operational modes. As we have to consider the

Re: [linux-sunxi] [PATCH v3 08/12] ASoC: sun4i-i2s: Add mclk enable regmap field

On Sat, Jul 29, 2017 at 10:17 PM, wrote: > From: Marcus Cooper > > The location of the mclk output enable bit is different on newer > SoCs. Use a regmap field to enable it. > > Signed-off-by: Marcus Cooper > --- >

Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

Hi Icenowy, Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng napisal(a): > Allwinner H3 features a "Display Engine 2.0". > > Add device tree bindings for the following parts: > - H3 TCONs > - H3 Mixers > - H3 Display engine > > Signed-off-by: Icenowy Zheng > --- >

[linux-sunxi] [PATCH] pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base

The V3s pin controller doesn't have the bank 0 (starts at address 0x200), which is like A33. However, this is not workarounded when developing the driver, which makes IRQ not working. Fix the IRQ bank base. Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC") Cc: sta...@vger.kernel.org

[linux-sunxi] [PATCH 13/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC

Orange Pi PC board has a HDMI-A port connected to the HDMI controller of Allwinner H3 SoC. Enable the HDMI output in Orange Pi PC device tree. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16 1 file changed, 16 insertions(+)

[linux-sunxi] [PATCH 12/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller

The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific glues. Add the related device nodes. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3.dtsi | 35 +++ 1 file changed, 35 insertions(+) diff --git

[linux-sunxi] [PATCH 00/13] Allwinner H3 DE2 basical support

Allwinner H3 features a "Display Engine 2.0", which needs some support to be present in the DRM driver. This patchset is now a basical version, which dropped some features I used to submitted: - TVE support (not so high priority now) - Multi-pipeline support (also not so high priority now due to

[linux-sunxi] [PATCH 04/13] drm: sun4i: add compatible for H3 display engine

Add a compatible string for H3 display engine in sun4i_drv code. Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index

[linux-sunxi] [PATCH 02/13] drm: sun4i: add support for H3 mixers

From: Icenowy Zheng Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels, and the other has 1 VI and 1 UI. There's also some graphics post-process function that is missing on mixer1, however, as we currently support none of these functions, the only

[linux-sunxi] [PATCH 06/13] clk: sunxi-ng: export CLK_PLL_DE for H3

The CLK_PLL_DE is needed to be referenced in device tree for H3, for both forcing the parent of PLL_DE. So export it to the device tree binding header. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +-- include/dt-bindings/clock/sun8i-h3-ccu.h |

[linux-sunxi] [PATCH 03/13] drm: sun4i: add support for H3's TCON

From: Icenowy Zheng Allwinner H3 has two special TCONs without channel 0. Add support for this kind of TCON. Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + drivers/gpu/drm/sun4i/sun4i_tcon.c | 43

[linux-sunxi] [PATCH 05/13] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3

Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the "Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE is a PLL for CLK_DE. Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also one part of the display clocks. So allow CLK_DE to set

[linux-sunxi] [PATCH 11/13] [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3

From: Jernej Skrabec Allwinner H3 features DesignWare HDMI Transmitter paired with custom PHY. For now, only video is supported by the driver. However, audio and CEC are also supported by the hardware. Signed-off-by: Jernej Skrabec ---

[linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

As we have already the support for the DE2 on Allwinner H3, add the display engine pipeline device tree nodes to its DTSI file. The H5 pipeline has some differences and will be enabled later. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3.dtsi | 170

[linux-sunxi] [PATCH 08/13] [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi

From: Jernej Skrabec Some custom phys don't support hpd interrupts. Add support for polling such events. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-)

[linux-sunxi] [PATCH 09/13] [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver

From: Jernej Skrabec Some platform glues of DesignWare HDMI controller require some initialization to be performed before probing the main HDMI controller. Add a pre_init function for this kind of work. Signed-off-by: Jernej Skrabec ---

[linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

From: Jernej Skrabec When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set. Add CLK_SET_RATE_PARENT flag for H3 HDMI clock. Signed-off-by: Jernej Skrabec Signed-off-by: Icenowy Zheng ---