On Wed, Jul 26, 2017 at 4:32 PM, Maxime Ripard
wrote:
> On Wed, Jul 26, 2017 at 04:28:23PM +0800, Chen-Yu Tsai wrote:
>> Hi everyone,
>>
>> This is v2 of my AXP813 support series. The device tree patches are
>> based on my A83T MMC support series. These will go
The bindings were not updated when the sun5i CCU driver was added in
commit 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver").
Signed-off-by: Jonathan Liu
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng wrote:
> Some new Allwinner SoCs' PRCM has a secure switch register, which
> controls the access to some clock and power registers in PRCM block.
>
> Add the definition of this register and its bits in the PRCM header
> file.
>
>
On Tue, Aug 1, 2017 at 4:54 PM, Icenowy Zheng wrote:
> The V3s pin controller doesn't have the bank 0 (starts at address
> 0x200), which is like A33. However, this is not workarounded when
> developing the driver, which makes IRQ not working.
>
> Fix the IRQ bank base.
>
>
在 2017-08-07 21:09,Linus Walleij 写道:
On Tue, Aug 1, 2017 at 4:54 PM, Icenowy Zheng wrote:
The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not workarounded when
developing the driver, which makes IRQ not working.
On Fri, May 12, 2017 at 10:22 PM, Maxime Ripard
wrote:
> On Fri, May 12, 2017 at 11:38:52AM +0200, Olliver Schinagl wrote:
>> This patch series adds support for the Olimex OLinuXino Lime2 eMMC. This
>> assembly variant uses eMMC flash instead of NAND (or no
On 1 August 2017 at 04:55, Chen-Yu Tsai wrote:
> On Sat, Jul 29, 2017 at 10:17 PM, wrote:
>> From: Marcus Cooper
>>
>> The BCLKDIV and MCLKDIV found on newer SoCs start from an offset of 1.
>> Add the functionality to adjust the
On 1 August 2017 at 10:31, Chen-Yu Tsai wrote:
> On Sat, Jul 29, 2017 at 10:17 PM, wrote:
>> From: Marcus Cooper
>>
>> On the original i2s block the channel mapping and selection were
>> configured for stereo audio by default: This is
在 2017-08-06 10:39,Chen-Yu Tsai 写道:
On Sat, Aug 05, 2017 at 05:35:55AM +0800, Icenowy Zheng wrote:
The configuration struct of A64 EMMC(MMC2) compatible used to
have the needs_new_timings variable missing, which lead to NULL
pointer dereference now when trying to set up the old timings mode, as
On Wed, 26 Jul 2017, Chen-Yu Tsai wrote:
> The X-Powers AXP813 PMIC is normally used with Allwinner's A83T SoC.
> It has the same range of functions as other X-Powers PMICs, such as
> DC-DC buck converter and linear regulator outputs, AC-IN and VBUS
> power supplies, power button trigger, GPIOs,
On Wed, 26 Jul 2017, Chen-Yu Tsai wrote:
> From: Quentin Schulz
>
> According to their datasheets, the AXP221, AXP223, AXP288, AXP803,
> AXP809 and AXP813 PEK have different values for startup time bits from
> the AXP20X, let's use the platform device id with
On Wed, 26 Jul 2017, Chen-Yu Tsai wrote:
> The binding already lists compatibles and regulators for the AXP806,
> but it is missing from the list of supported chips at the beginning.
>
> Add it.
>
> Fixes: 204ae2963e10 ("mfd: axp20x: Add bindings for AXP806 PMIC")
> Signed-off-by: Chen-Yu Tsai
On Wed, 26 Jul 2017, Chen-Yu Tsai wrote:
> The X-Powers AXP813 is a PMIC designed to be paired with Allwinner's
> A83T SoC. There is also an AXP818, which is paired with the H8 SoC.
>
> The two models seem to be identical, apart from the external markings.
>
> This patch introduces the basic
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