在 2017-09-18 16:30,Maxime Ripard 写道:
On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:
于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard
写到:
>On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
>> Allwinner H3 features a thermal sensor
On Montag, 18. September 2017 10:11:34 CEST Maxime Ripard wrote:
> On Sun, Sep 17, 2017 at 05:19:52AM +0200, Stefan Brüns wrote:
> > The A64 is register compatible with the H3, but has a different number
> > of dma channels and request ports.
> >
> > Attach additional properties to the node to
On Mon, Sep 11, 2017 at 11:55:26PM +0800, Icenowy Zheng wrote:
> As we're going to add simplefb support for Allwinner SoCs with DE2, add
> suitable pipeline strings in the device tree binding.
>
> Signed-off-by: Icenowy Zheng
> ---
>
On 06/07/17 10:23, Alexander Graf wrote:
Hi,
> On 07/06/2017 11:14 AM, Andre Przywara wrote:
>> The UEFI spec allows an EFI system partition (ESP, with the bootloader or
>> kernel EFI apps on it) to reside on a disk using a "legacy" MBR
>> partitioning scheme.
>> But in contrast to actual legacy
Hi,
On Fri, Sep 15, 2017 at 09:59:20AM +0800, Icenowy Zheng wrote:
> Add an option to indicate that the video driver should setup a SimpleFB
> node that passes the video framebuffer initialized by U-Boot to the
> operating system kernel.
>
> Currently only the Allwinner DE2 driver uses this
于 2017年9月18日 GMT+08:00 下午3:29:06, Maxime Ripard
写到:
>Hi,
>
>On Fri, Sep 15, 2017 at 09:59:20AM +0800, Icenowy Zheng wrote:
>> Add an option to indicate that the video driver should setup a
>SimpleFB
>> node that passes the video framebuffer initialized by
On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a thermal sensor like the one in A33, but has its
> register re-arranged, the clock divider moved to CCU (originally the
> clock divider is in ADC) and added a pair of bus clock and reset.
>
> Update the
On Thu, Sep 14, 2017 at 10:52:48PM +0800, Icenowy Zheng wrote:
> The SoCs after H3 has newer thermal sensor ADCs, which have two clock
> inputs (bus clock and sampling clock) and a reset. The registers are
> also re-arranged.
>
> This commit reworks the code, adds the process of the clocks and
>
On Thu, Sep 14, 2017 at 10:52:47PM +0800, Icenowy Zheng wrote:
> As the H3 SoC, which is also in sun8i line, has totally different
> register map for the thermal sensor (a cut down version of GPADC), we
> should rename A23/A33-specified registers to contain A33, in order to
> prevent obfuscation
于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard
写到:
>On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
>> Allwinner H3 features a thermal sensor like the one in A33, but has
>its
>> register re-arranged, the clock divider moved to CCU (originally
Hi,
On Sun, Sep 17, 2017 at 05:19:47AM +0200, Stefan Brüns wrote:
> The H83T uses a compatible string different from the A23, but requires
> the same clock autogating register setting.
>
> The H3 also requires setting the clock autogating register, but has
> the register at a different offset.
>
On Sun, Sep 17, 2017 at 05:19:48AM +0200, Stefan Brüns wrote:
> For the H3, the burst lengths field offsets in the channel configuration
> register differs from earlier SoC generations.
>
> Using the A31 register macros actually configured the H3 controller
> do to bursts of length 1 always,
On Sun, Sep 17, 2017 at 05:19:49AM +0200, Stefan Brüns wrote:
> The current code mixes three distinct operations when transforming
> the slave config to register settings:
>
> 1. special handling of DMA_SLAVE_BUSWIDTH_UNDEFINED, maxburst == 0
> 2. range checking
> 3. conversion of raw to
On Sun, Sep 17, 2017 at 05:19:50AM +0200, Stefan Brüns wrote:
> The H3 supports bursts lengths of 1, 4, 8 and 16 transfers, each with
> a width of 1, 2, 4 or 8 bytes.
>
> The register value for the the width is log2-encoded, change the
> conversion function to provide the correct value for width
On Sun, Sep 17, 2017 at 05:19:52AM +0200, Stefan Brüns wrote:
> The A64 is register compatible with the H3, but has a different number
> of dma channels and request ports.
>
> Attach additional properties to the node to allow future reuse of the
> compatible for controllers with different number
1;4803;0c
On Sun, Sep 17, 2017 at 05:19:51AM +0200, Stefan Brüns wrote:
> Preparatory patch: If the same compatible is used for different SoCs which
> have a common register layout, but different number of channels, the
> channel count can no longer be stored in the config. Store it in the
>
Hi,
On Sun, Sep 17, 2017 at 05:19:53AM +0200, Stefan Brüns wrote:
> + ret = of_property_read_u32(np, "dma-channels", >num_pchans);
> + if (ret && !sdc->num_pchans) {
> + dev_err(>dev, "Can't get dma-channels.\n");
> + return ret;
> + }
> +
> + if
On Sun, Sep 17, 2017 at 05:19:54AM +0200, Stefan Brüns wrote:
> The A64 SoC has the same dma engine as the H3 (sun8i), with a
> reduced amount of physical channels. To allow future reuse of the
> compatible, leave the channel count etc. in the config data blank
> and retrieve it from the
On Mon, Sep 18, 2017 at 03:31:54PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年9月18日 GMT+08:00 下午3:29:06, Maxime Ripard
> 写到:
> >Hi,
> >
> >On Fri, Sep 15, 2017 at 09:59:20AM +0800, Icenowy Zheng wrote:
> >> Add an option to indicate that the video driver should
On Thu, Sep 14, 2017 at 10:52:50PM +0800, Icenowy Zheng wrote:
> As we have gained the support for the thermal sensor in H3, we can now
> add its device nodes to the device tree.
>
> Add them to the H3 device tree.
>
> The calibration data of the thermal sensor is still not added, as
> it's
On Sat, Sep 16, 2017 at 06:14:08PM +0800, icen...@aosc.io wrote:
> > The H3 apparently supports IRQs, why do you not support them for the
> > temperature? They might be broken as it is on A33 but then it might be a
> > good idea to write it down in a comment in the driver (and not adding
> > the
Hi Jonathan,
On Sat, Sep 16, 2017 at 03:17:34PM -0700, Jonathan Cameron wrote:
> On Sat, 16 Sep 2017 12:05:49 +0200
> Quentin Schulz wrote:
>
> > Hi Icenowy,
> >
> > On 14/09/2017 16:52, Icenowy Zheng wrote:
> > > Because of the restriction of the OF thermal
On Thu, 14 Sep 2017, Icenowy Zheng wrote:
> As the H3 SoC, which is also in sun8i line, has totally different
> register map for the thermal sensor (a cut down version of GPADC), we
> should rename A23/A33-specified registers to contain A33, in order to
> prevent obfuscation with H3 registers.
On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:
> 于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard
> 写到:
> >On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
> >> Allwinner H3 features a thermal sensor like the one in A33, but has
>
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