On Mon, Feb 26, 2018 at 5:38 PM, Maxime Ripard
wrote:
> Hi,
>
> On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote:
>> Some NM PLLs doesn't work well when their output clock rate is set below
>> certain rate.
>>
>> Add support for that constrain.
>
> In such
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot.
The bug is there since v4.16-rc1 and appeared after the clk branch was
merged.
You can find the shortend trace below:
Unable to handle kernel NULL pointer dereference at virtual address
pgd =
On 19.02.2018 09:10, Maxime Ripard wrote:
On Sat, Feb 17, 2018 at 03:22:35PM +0100, Philipp Rossak wrote:
Right now the performance govenor is the default frequency govenor on
sunxi devices. This causes some general problems.
When the cpu is idle the cpu runs with its maximum frequency.
This
Hi Jernej,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on next-20180226]
[cannot apply to robh/for-next v4.16-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system
Hi,
On Mon, 26 Feb 2018 12:06:37 +0100
Hans Verkuil wrote:
> Hi all,
>
> On 01/30/2018 03:48 AM, Yong wrote:
> > Hi,
> >
> > On Mon, 29 Jan 2018 13:49:14 -0800
> > Randy Dunlap wrote:
> >
> >> On 01/29/2018 01:21 AM, Yong Deng wrote:
> >>>
This patchset add initial support for Allwinner V3s CSI.
Allwinner V3s SoC features two CSI module. CSI0 is used for MIPI CSI-2
interface and CSI1 is used for parallel interface. This is not
documented in datasheet but by test and guess.
This patchset implement a v4l2 framework driver and add a
Add binding documentation for Allwinner V3s CSI.
Acked-by: Maxime Ripard
Acked-by: Sakari Ailus
Reviewed-by: Rob Herring
Signed-off-by: Yong Deng
---
Hi Jernej,
On Tue, Feb 27, 2018 at 3:27 AM, Jernej Škrabec wrote:
> Hi,
>
> Dne ponedeljek, 26. februar 2018 ob 17:21:05 CET je Icenowy Zheng napisal(a):
>> 于 2018年2月27日 GMT+08:00 上午12:16:44, "Jernej Škrabec"
> 写到:
>> >Hi Julian,
>> >
>> >Dne
Allwinner V3s SoC features two CSI module. CSI0 is used for MIPI CSI-2
interface and CSI1 is used for parallel interface. This is not
documented in datasheet but by test and guess.
This patch implement a v4l2 framework driver for it.
Currently, the driver only support the parallel interface.
Hi all,
On 01/30/2018 03:48 AM, Yong wrote:
> Hi,
>
> On Mon, 29 Jan 2018 13:49:14 -0800
> Randy Dunlap wrote:
>
>> On 01/29/2018 01:21 AM, Yong Deng wrote:
>>> Allwinner V3s SoC features two CSI module. CSI0 is used for MIPI CSI-2
>>> interface and CSI1 is used for
On Mon, Feb 26, 2018 at 6:25 PM, Maxime Ripard
wrote:
> On Mon, Feb 26, 2018 at 05:43:01PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Feb 26, 2018 at 5:38 PM, Maxime Ripard
>> wrote:
>> > Hi,
>> >
>> > On Sat, Feb 24, 2018 at 10:45:31PM +0100,
On 02/26/18 03:26, Maxime Ripard wrote:
> On Fri, Feb 23, 2018 at 11:22:06PM +0800, Icenowy Zheng wrote:
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
>>>
>>> Is it needed? The bootloader should fill it with whatever version it
>>> has,
Hi Julian,
Dne nedelja, 25. februar 2018 ob 09:11:34 CET je Julian Calaby napisal(a):
> Hi Jernej,
>
> On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec
wrote:
> > Enable HDMI output on all boards which have HDMI connector.
> >
> > Signed-off-by: Jernej Skrabec
Hi there,
currently I am using Olimex A20-LIME2 board with the OLinuXino-A20 Linux
and kernel version 3.4.103-00033-g9a1cd03-dirty . I wanted to emulate my
board as a Keyboard when it connect to a HOST PC and to do so I followed
theses instruction here to pass platform_device structure to
Hi,
Dne ponedeljek, 26. februar 2018 ob 10:38:00 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote:
> > Some NM PLLs doesn't work well when their output clock rate is set below
> > certain rate.
> >
> > Add support for that constrain.
>
>
Hi,
Dne ponedeljek, 26. februar 2018 ob 10:39:30 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, Feb 24, 2018 at 10:45:38PM +0100, Jernej Skrabec wrote:
> > Current polarity configuration code is cleary wrong since it compares
> > same flag two times. However, even if flag name is fixed, it
于 2018年2月27日 GMT+08:00 上午12:16:44, "Jernej Škrabec"
写到:
>Hi Julian,
>
>Dne nedelja, 25. februar 2018 ob 09:11:34 CET je Julian Calaby
>napisal(a):
>> Hi Jernej,
>>
>> On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec
>
>wrote:
>> > Enable HDMI
Hi all,
Dne sobota, 24. februar 2018 ob 22:45:41 CET je Jernej Skrabec napisal(a):
> While A83T HDMI PHY seems to be just customized Synopsys HDMI PHY, H3
> HDMI PHY is completely custom PHY.
>
> However, they still have many things in common like clock and reset
> setup, setting sync polarity
Hi,
Dne ponedeljek, 26. februar 2018 ob 17:21:05 CET je Icenowy Zheng napisal(a):
> 于 2018年2月27日 GMT+08:00 上午12:16:44, "Jernej Škrabec"
写到:
> >Hi Julian,
> >
> >Dne nedelja, 25. februar 2018 ob 09:11:34 CET je Julian Calaby
> >
> >napisal(a):
> >> Hi Jernej,
> >>
> >>
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