[linux-sunxi] [PATCH v6 4/4] arm64: defconfig: Enable PWM_SUN4I
Allwinner PWM support need for ARM64 Allwinner SoC's which used pwms, builds it as module. Signed-off-by: Jagan Teki --- Changes for v6: - none Changes for v5: - new patch arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index cb614bd70716..dfdbc0646472 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -648,6 +648,7 @@ CONFIG_PWM_MESON=m CONFIG_PWM_RCAR=m CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_SAMSUNG=y +CONFIG_PWM_SUN4I=m CONFIG_PWM_TEGRA=m CONFIG_RESET_TI_SCI=y CONFIG_PHY_XGENE=y -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v4 25/26] [DO NOT MERGE] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel
This patch add support for Bananapi S070WV20-CT16 DSI panel to
BPI-M64 board.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC1 as DVDD supply
- PD6 gpio for reset pin
- PD5 gpio for backlight enable pin
- PD7 gpio for backlight vdd supply
Signed-off-by: Jagan Teki
---
.../dts/allwinner/sun50i-a64-bananapi-m64.dts | 42 +++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index ef1c90401bb2..6cb010e3bbd9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -45,6 +45,7 @@
#include "sun50i-a64.dtsi"
#include
+#include
/ {
model = "BananaPi-M64";
@@ -56,6 +57,15 @@
serial1 =
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <_pwm 0 5 PWM_POLARITY_INVERTED>;
+ brightness-levels = <1 2 4 8 16 32 64 128 512>;
+ default-brightness-level = <2>;
+ enable-gpios = < 3 5 GPIO_ACTIVE_HIGH>; /* LCD-BL-EN: PD5 */
+ power-supply = <_vdd_backlight>;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -91,6 +101,15 @@
};
};
+ reg_vdd_backlight: vdd-backlight {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-backlight";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 3 7 GPIO_ACTIVE_HIGH>; /* LCD-PWR-EN: PD7 */
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
@@ -101,6 +120,23 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+
+ panel@0 {
+ compatible = "bananapi,s070wv20-ct16-icn6211";
+ reg = <0>;
+ avdd-supply = <_dc1sw>;
+ dvdd-supply = <_dldo1>;
+ reset-gpios = < 3 6 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD6 */
+ backlight = <>;
+ };
+};
+
{
status = "okay";
};
@@ -193,6 +229,12 @@
status = "okay";
};
+_pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pwm_pin>;
+ status = "okay";
+};
+
_rsb {
status = "okay";
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 23/26] dt-bindings: sun6i-dsi: Add compatible for A64 DPHY
The MIPI DSI PHY HDMI controller on Allwinner A64 is similar on the one on A31. Add A64 compatible and append A31 compatible as fallback. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt index adc7cdf129dd..08f1f57abff5 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt @@ -40,6 +40,7 @@ D-PHY Required properties: - compatible: value must be one of: * allwinner,sun6i-a31-mipi-dphy +* "allwinner,sun50i-a64-mipi-dphy", "allwinner,sun6i-a31-mipi-dphy" - reg: base address and size of memory-mapped region - clocks: phandles to the clocks feeding the DSI encoder * bus: the DSI interface clock -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v4 20/26] dt-bindings: panel: Add Techstar TS8550B MIPI-DSI panel
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
LCD panel. Add dt-bingings for it.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
.../display/panel/techstar,ts8550b.txt| 22 +++
1 file changed, 22 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/techstar,ts8550b.txt
diff --git
a/Documentation/devicetree/bindings/display/panel/techstar,ts8550b.txt
b/Documentation/devicetree/bindings/display/panel/techstar,ts8550b.txt
new file mode 100644
index ..9d3056dd8bf9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/techstar,ts8550b.txt
@@ -0,0 +1,22 @@
+Techstar TS8550B MIPI-DSI LCD Panel
+
+Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI LCD panel.
+
+Required properties:
+- compatible: must be "techstar,ts8550b"
+- reg: DSI virtual channel used by that screen
+- avdd-supply: analog regulator dc1 switch
+- dvdd-supply: 3v3 digital regulator
+- reset-gpios: a GPIO phandle for the reset pin
+
+Optional properties:
+- backlight: phandle for the backlight control.
+
+panel@0 {
+ compatible = "techstar,ts8550b";
+ reg = <0>;
+ avdd-supply = <_dc1sw>;
+ dvdd-supply = <_dldo2>;
+ reset-gpios = < 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ backlight = <>;
+};
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 26/26] arm64: dts: allwinner: a64-amarula-relic: Enable Techstar TS8550B MIPI-DSI panel
Amarula A64-Relic board by default bound with Techstar TS8550B
MIPI-DSI panel, add support for it.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC2 as DVDD supply
- DCDC1 as VCC-DSI supply
- PD24 gpio for reset pin
- PD23 gpio for backlight enable pin
Signed-off-by: Jagan Teki
---
.../allwinner/sun50i-a64-amarula-relic.dts| 46 +++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
index 6cb2b7f0c817..ecc0d8094815 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
@@ -9,6 +9,7 @@
#include "sun50i-a64.dtsi"
#include
+#include
/ {
model = "Amarula A64-Relic";
@@ -18,6 +19,14 @@
serial0 =
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = < 0 5 PWM_POLARITY_INVERTED>;
+ brightness-levels = <1 2 4 8 16 32 64 128 512>;
+ default-brightness-level = <2>;
+ enable-gpios = < 3 23 GPIO_ACTIVE_HIGH>; /* LCD-BL-EN: PD23
*/
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -30,6 +39,28 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ vcc-dsi-supply = <_dldo1>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "techstar,ts8550b";
+ reg = <0>;
+ avdd-supply = <_dc1sw>;
+ dvdd-supply = <_dldo2>;
+ reset-gpios = < 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */
+ backlight = <>;
+ };
+};
+
{
status = "okay";
};
@@ -72,6 +103,12 @@
status = "okay";
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ status = "okay";
+};
+
_rsb {
status = "okay";
@@ -107,6 +144,15 @@
regulator-name = "vcc-pll-avcc";
};
+_dc1sw {
+ /*
+* This regulator also indirectly drives the PD pingroup GPIOs,
+* which also controls the power LED.
+*/
+ regulator-always-on;
+ regulator-name = "vcc-phy";
+};
+
_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <330>;
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 21/26] drm/panel: Add Techstar TS8550B MIPI-DSI LCD panel
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
LCD panel. Add panel driver for it.
Signed-off-by: Jagan Teki
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1 +
.../gpu/drm/panel/panel-techstar-ts8550b.c| 324 ++
4 files changed, 340 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-techstar-ts8550b.c
diff --git a/MAINTAINERS b/MAINTAINERS
index f5bb2ffa1089..3dac08d0b3cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4718,6 +4718,12 @@ S: Maintained
F: drivers/gpu/drm/tinydrm/st7735r.c
F: Documentation/devicetree/bindings/display/sitronix,st7735r.txt
+DRM DRIVER FOR TECHSTAR TS8550B MIPI-DSI LCD PANELS
+M: Jagan Teki
+S: Maintained
+F: drivers/gpu/drm/panel/panel-techstar-ts8550b.c
+F: Documentation/devicetree/bindings/display/panel/techstar,ts8550b.txt
+
DRM DRIVER FOR TDFX VIDEO CARDS
S: Orphan / Obsolete
F: drivers/gpu/drm/tdfx/
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 20b88c275421..d0d4e60f5153 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -195,4 +195,13 @@ config DRM_PANEL_SITRONIX_ST7789V
Say Y here if you want to enable support for the Sitronix
ST7789V controller for 240x320 LCD panels
+config DRM_PANEL_TECHSTAR_TS8550B
+ tristate "Techstar TS8550B MIPI-DSI panel driver"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y if you want to enable support for panels based on the
+ Techstar TS8550B MIPI-DSI interface.
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 04696bb85218..88011f06edb8 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o
obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
+obj-$(CONFIG_DRM_PANEL_TECHSTAR_TS8550B) += panel-techstar-ts8550b.o
diff --git a/drivers/gpu/drm/panel/panel-techstar-ts8550b.c
b/drivers/gpu/drm/panel/panel-techstar-ts8550b.c
new file mode 100644
index ..70a5f8ec6908
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-techstar-ts8550b.c
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Amarula Solutions.
+ * Author: Jagan Teki
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+
+struct techstar {
+ struct drm_panelpanel;
+ struct mipi_dsi_device *dsi;
+
+ struct backlight_device *backlight;
+ struct regulator*dvdd;
+ struct regulator*avdd;
+ struct gpio_desc*reset;
+};
+
+static inline struct techstar *panel_to_techstar(struct drm_panel *panel)
+{
+ return container_of(panel, struct techstar, panel);
+}
+
+static inline int techstar_dcs_write_seq(struct techstar *ctx, const void *seq,
+ size_t len)
+{
+ return mipi_dsi_dcs_write_buffer(ctx->dsi, seq, len);
+};
+
+#define techstar_dcs_write_seq_static(ctx, seq...) \
+ ({ \
+ static const u8 d[] = { seq }; \
+ techstar_dcs_write_seq(ctx, d, ARRAY_SIZE(d)); \
+ })
+
+static void techstar_init_sequence(struct techstar *ctx)
+{
+ techstar_dcs_write_seq_static(ctx, MIPI_DCS_SOFT_RESET, 0x00);
+ msleep(200);
+ techstar_dcs_write_seq_static(ctx, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x11);
+ techstar_dcs_write_seq_static(ctx, 0xD1, 0x11);
+ techstar_dcs_write_seq_static(ctx, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
+ msleep(200);
+ techstar_dcs_write_seq_static(ctx, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x10);
+ techstar_dcs_write_seq_static(ctx, 0xC0, 0xE9, 0x03);
+ techstar_dcs_write_seq_static(ctx, 0xC1, 0x12, 0x02);
+ techstar_dcs_write_seq_static(ctx, 0xC2, 0x07, 0x06);
+ techstar_dcs_write_seq_static(ctx, 0xB0, 0x00, 0x0E, 0x15, 0x0F, 0x11,
+0x08, 0x08, 0x08, 0x08, 0x23, 0x04, 0x13,
+0x12, 0x2B, 0x34, 0x1F);
+ techstar_dcs_write_seq_static(ctx, 0xB1, 0x00, 0x0E, 0x95, 0x0F, 0x13,
+0x07, 0x09, 0x08, 0x08, 0x22, 0x04, 0x10,
+0x0E, 0x2C, 0x34, 0x1F);
+ techstar_dcs_write_seq_static(ctx, 0xFF, 0x77, 0x01, 0x00, 0x00, 0x11);
+ techstar_dcs_write_seq_static(ctx, 0xB0, 0x45);
+ techstar_dcs_write_seq_static(ctx, 0xB1, 0x13);
+
[linux-sunxi] [PATCH v4 24/26] arm64: dts: allwinner: a64: Add DSI pipeline
The A64 has a MIPI-DSI block which is similar to A31
without mod clock.
So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper DSI pipeline.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45 +++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index f3a66f888205..d6f269883759 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -320,6 +320,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ tcon0_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint =
<_in_tcon0>;
+ allwinner,tcon-channel = <1>;
+ };
};
};
};
@@ -829,6 +835,45 @@
status = "disabled";
};
+ dsi: dsi@1ca {
+ compatible = "allwinner,sun50i-a64-mipi-dsi";
+ reg = <0x01ca 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_MIPI_DSI>;
+ clock-names = "bus";
+ resets = < RST_BUS_MIPI_DSI>;
+ phys = <>;
+ phy-names = "dphy";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dsi_in_tcon0: endpoint {
+ remote-endpoint =
<_out_dsi>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1ca1000 {
+ compatible = "allwinner,sun50i-a64-mipi-dphy",
+"allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01ca1000 0x1000>;
+ clocks = < CLK_BUS_MIPI_DSI>,
+< CLK_DSI_DPHY>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_MIPI_DSI>;
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
hdmi: hdmi@1ee {
compatible = "allwinner,sun50i-a64-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi";
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 22/26] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI
Manual noted to use PLL_MIPI rate 500MHz to 1.4GHz,
but lowering the min rate by 300MHz can result proper
working nkms divider with the help of desired dclock
rate from panel driver.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 019d67bf97c4..5a3a5b821f8b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -167,6 +167,8 @@ static struct ccu_nkm pll_mipi_clk = {
.n = _SUNXI_CCU_MULT(8, 4),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.m = _SUNXI_CCU_DIV(0, 4),
+ .min_rate = 3,/* Actual rate is 500MHz */
+ .max_rate = 14UL,
.common = {
.reg= 0x040,
.hw.init= CLK_HW_INIT("pll-mipi", "pll-video0",
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 19/26] drm/panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge
Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge
panel which can be used to connect via DSI port on BPI-M64 board,
so add a driver for it.
The same panel PCB comes with parallel RBG which is supported via
panel-simple driver with "bananapi,s070wv20-ct16" compatible.
BSP dclock of 30MHz is not working with existing sunxi-ng and sun4i
sun4i_dclk_recalc, so updated to 55MHz can result proper working
nkm dividers.
Signed-off-by: Jagan Teki
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1 +
.../panel/panel-bananapi-s070wv20-icn6211.c | 298 ++
4 files changed, 314 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c
diff --git a/MAINTAINERS b/MAINTAINERS
index a25549205cc1..f5bb2ffa1089 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4601,6 +4601,12 @@ M: Dave Airlie
S: Odd Fixes
F: drivers/gpu/drm/ast/
+DRM DRIVER FOR BANANAPI S070WV20-CT16 ICN6211 MIPI-DSI TO RGB PANELS
+M: Jagan Teki
+S: Maintained
+F: drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c
+F:
Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt
+
DRM DRIVER FOR BOCHS VIRTUAL GPU
M: Gerd Hoffmann
L: virtualizat...@lists.linux-foundation.org
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 6020c30a33b3..20b88c275421 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -17,6 +17,15 @@ config DRM_PANEL_ARM_VERSATILE
reference designs. The panel is detected using special registers
in the Versatile family syscon registers.
+config DRM_PANEL_BANANAPI_S070WV20_ICN6211
+ tristate "Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge panel
driver"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y if you want to enable support for panels based on the
+ Bananapi S070WV20-CT16 MIPI-DSI controller.
+
config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 5ccaaa9d13af..04696bb85218 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BANANAPI_S070WV20_ICN6211) +=
panel-bananapi-s070wv20-icn6211.o
obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o
diff --git a/drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c
b/drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c
new file mode 100644
index ..10174495a6c8
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Amarula Solutions
+ * Author: Jagan Teki
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+
+struct s070wv20 {
+ struct drm_panelpanel;
+ struct mipi_dsi_device *dsi;
+
+ struct backlight_device *backlight;
+ struct regulator*dvdd;
+ struct regulator*avdd;
+ struct gpio_desc*reset;
+};
+
+static inline struct s070wv20 *panel_to_s070wv20(struct drm_panel *panel)
+{
+ return container_of(panel, struct s070wv20, panel);
+}
+
+struct s070wv20_init_cmd {
+ size_t len;
+ const char *data;
+};
+
+#define S070WV20_INIT_CMD(...) { \
+ .len = sizeof((char[]){__VA_ARGS__}), \
+ .data = (char[]){__VA_ARGS__} }
+
+static const struct s070wv20_init_cmd s070wv20_init_cmds[] = {
+ S070WV20_INIT_CMD(0x7A, 0xC1),
+ S070WV20_INIT_CMD(0x20, 0x20),
+ S070WV20_INIT_CMD(0x21, 0xE0),
+ S070WV20_INIT_CMD(0x22, 0x13),
+ S070WV20_INIT_CMD(0x23, 0x28),
+ S070WV20_INIT_CMD(0x24, 0x30),
+ S070WV20_INIT_CMD(0x25, 0x28),
+ S070WV20_INIT_CMD(0x26, 0x00),
+ S070WV20_INIT_CMD(0x27, 0x0D),
+ S070WV20_INIT_CMD(0x28, 0x03),
+ S070WV20_INIT_CMD(0x29, 0x1D),
+ S070WV20_INIT_CMD(0x34, 0x80),
+ S070WV20_INIT_CMD(0x36, 0x28),
+ S070WV20_INIT_CMD(0xB5, 0xA0),
+ S070WV20_INIT_CMD(0x5C, 0xFF),
+ S070WV20_INIT_CMD(0x2A, 0x01),
+ S070WV20_INIT_CMD(0x56, 0x92),
+ S070WV20_INIT_CMD(0x6B, 0x71),
+ S070WV20_INIT_CMD(0x69, 0x2B),
+ S070WV20_INIT_CMD(0x10, 0x40),
+ S070WV20_INIT_CMD(0x11, 0x98),
+ S070WV20_INIT_CMD(0xB6, 0x20),
+ S070WV20_INIT_CMD(0x51, 0x20),
+ S070WV20_INIT_CMD(0x09, 0x10),
+};
+
+static int s070wv20_prepare(struct drm_panel *panel)
+{
+ struct s070wv20 *ctx =
[linux-sunxi] [PATCH v4 17/26] dt-bindings: sun6i-dsi: Add VCC-DSI supply property
Most of the Allwinner MIPI DSI controllers are supply with VCC-DSI pin. which need to supply for some of the boards to trigger the power. So, document the supply property so-that the required board can eable it via device tree. Signed-off-by: Jagan Teki --- Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt index 9fa6e7a758ad..adc7cdf129dd 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt @@ -28,6 +28,9 @@ Required properties: first port should be the input endpoint, usually coming from the associated TCON. +Optional properties: + - vcc-dsi-supply: the VCC-DSI power supply of the DSI encoder + Any MIPI-DSI device attached to this should be described according to the bindings defined in ../mipi-dsi-bus.txt -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v4 04/26] drm/sun4i: sun6i_mipi_dsi: Add has_mod_clk quirk
Mod clock is not mandatory for all Allwinner MIPI DSI
controllers, it is connected as CLK_DSI_SCLK for A31
and not available in A64.
So add has_mod_clk quirk and process the clk accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 39 ++
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 5
2 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index e3b34a345546..561de393ea23 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -981,6 +982,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
dsi->host.ops = _dsi_host_ops;
dsi->host.dev = dev;
+ dsi->variant = of_device_get_match_data(dev);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base)) {
@@ -1001,17 +1004,20 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
return PTR_ERR(dsi->reset);
}
- dsi->mod_clk = devm_clk_get(dev, "mod");
- if (IS_ERR(dsi->mod_clk)) {
- dev_err(dev, "Couldn't get the DSI mod clock\n");
- return PTR_ERR(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk) {
+ dsi->mod_clk = devm_clk_get(dev, "mod");
+ if (IS_ERR(dsi->mod_clk)) {
+ dev_err(dev, "Couldn't get the DSI mod clock\n");
+ return PTR_ERR(dsi->mod_clk);
+ }
}
/*
* In order to operate properly, that clock seems to be always
* set to 297MHz.
*/
- clk_set_rate_exclusive(dsi->mod_clk, 29700);
+ if (dsi->variant->has_mod_clk)
+ clk_set_rate_exclusive(dsi->mod_clk, 29700);
dphy_node = of_parse_phandle(dev->of_node, "phys", 0);
ret = sun6i_dphy_probe(dsi, dphy_node);
@@ -1043,7 +1049,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
pm_runtime_disable(dev);
sun6i_dphy_remove(dsi);
err_unprotect_clk:
- clk_rate_exclusive_put(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk)
+ clk_rate_exclusive_put(dsi->mod_clk);
return ret;
}
@@ -1056,7 +1063,8 @@ static int sun6i_dsi_remove(struct platform_device *pdev)
mipi_dsi_host_unregister(>host);
pm_runtime_disable(dev);
sun6i_dphy_remove(dsi);
- clk_rate_exclusive_put(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk)
+ clk_rate_exclusive_put(dsi->mod_clk);
return 0;
}
@@ -1066,7 +1074,8 @@ static int __maybe_unused sun6i_dsi_runtime_resume(struct
device *dev)
struct sun6i_dsi *dsi = dev_get_drvdata(dev);
reset_control_deassert(dsi->reset);
- clk_prepare_enable(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk)
+ clk_prepare_enable(dsi->mod_clk);
/*
* Enable the DSI block.
@@ -1094,7 +1103,8 @@ static int __maybe_unused
sun6i_dsi_runtime_suspend(struct device *dev)
{
struct sun6i_dsi *dsi = dev_get_drvdata(dev);
- clk_disable_unprepare(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk)
+ clk_disable_unprepare(dsi->mod_clk);
reset_control_assert(dsi->reset);
return 0;
@@ -1106,9 +1116,16 @@ static const struct dev_pm_ops sun6i_dsi_pm_ops = {
NULL)
};
+static const struct sun6i_dsi_variant sun6i_a31_dsi = {
+ .has_mod_clk = true,
+};
+
static const struct of_device_id sun6i_dsi_of_table[] = {
- { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
- { }
+ {
+ .compatible = "allwinner,sun6i-a31-mipi-dsi",
+ .data = _a31_dsi,
+ },
+ { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
index dbbc5b3ecbda..597b62227019 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
@@ -20,6 +20,10 @@ struct sun6i_dphy {
struct reset_control*reset;
};
+struct sun6i_dsi_variant {
+ boolhas_mod_clk;
+};
+
struct sun6i_dsi {
struct drm_connectorconnector;
struct drm_encoder encoder;
@@ -35,6 +39,7 @@ struct sun6i_dsi {
struct sun4i_drv*drv;
struct mipi_dsi_device *device;
struct drm_panel*panel;
+ const struct sun6i_dsi_variant *variant;
};
static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
--
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[linux-sunxi] [PATCH v4 09/26] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits
TCON DRQ set bits for non-burst DSI mode can computed via
horizontal front porch instead of front porch + sync timings.
BSP code form BPI-M64-bsp is computing TCON DRQ set bits
for non-burts as (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
=> panel->lcd_ht -panel->lcd_x - panel->lcd_hbp
=> (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x)
- panel->lcd_x - panel->hbp
=> timmings->hor_front_porch
=> mode->hsync_start - mode->hdisplay
So, update the DRQ set bits accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index eeea977604ac..fc4252d96c38 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
struct mipi_dsi_device *device = dsi->device;
u32 val = 0;
- if ((mode->hsync_end - mode->hdisplay) > 20) {
+ if ((mode->hsync_start - mode->hdisplay) > 20) {
/* Maagic */
- u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
+ u16 drq = (mode->hsync_start - mode->hdisplay) - 20;
drq *= mipi_dsi_pixel_format_to_bpp(device->format);
drq /= 32;
--
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[linux-sunxi] [PATCH v4 18/26] dt-bindings: panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge
Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB
bridge panel, which is available on same PCB with 24-bit RGB interface.
So, this patch adds DSI specific binding details on existing
dt-bindings file.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
.../display/panel/bananapi,s070wv20-ct16.txt | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt
b/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt
index 35bc0c839f49..b7855dc7c66f 100644
--- a/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt
+++ b/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt
@@ -1,12 +1,39 @@
Banana Pi 7" (S070WV20-CT16) TFT LCD Panel
+S070WV20-CT16 is 7" 800x480 panel connected through a 24-bit RGB interface.
+
+Depending on the variant, the PCB attached to the panel module either
+supports DSI, or DSI + 24-bit RGB. DSI is converted to 24-bit RGB via
+an onboard ICN6211 MIPI DSI - RGB bridge chip, then fed to the panel
+itself
+
Required properties:
-- compatible: should be "bananapi,s070wv20-ct16"
+- compatible:
+ for 24-bit RGB interface, use "bananapi,s070wv20-ct16"
+ for ICN6211 MIPI-DSI to RGB bridge, use "bananapi,s070wv20-ct16-icn6211"
+
+Required properties for RGB:
- power-supply: see ./panel-common.txt
+Required properties for MIPI-DSI to RGB:
+- reg: for DSI virtual channel used by that screen
+- avdd-supply: analog regulator dc1 switch
+- dvdd-supply: 3v3 digital regulator
+- reset-gpios: a GPIO phandle for the reset pin
+
Optional properties:
-- enable-gpios: see ./simple-panel.txt
+- enable-gpios: see ./simple-panel.txt(not available in MIPI-DSI to RGB bridge)
- backlight: see ./simple-panel.txt
This binding is compatible with the simple-panel binding, which is specified
in ./simple-panel.txt.
+
+Example:
+panel@0 {
+ compatible = "bananapi,s070wv20-ct16-icn6211";
+ reg = <0>;
+ avdd-supply = <_dc1sw>;
+ dvdd-supply = <_dldo1>;
+ reset-gpios = < 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ backlight = <_dsi>;
+};
--
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[linux-sunxi] [PATCH v4 11/26] drm/sun4i: sun6i_mipi_dsi: Fix DSI hbp timing value
Current driver is calculating hbp maximum value by subtracting hsync_start with hdisplay which is front porch value, but the hbp refers to back porch. Back porch value is calculating by subtracting htotal with hsync_end as per drm_mode timings, and BSP code from BPI-M64-bsp is eventually following the same. BPI-M64-bsp is computing hbp as (in drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c) dsi_hbp = (hbp-hspw)*dsi_pixel_bits[format]/8 - (4+2); => (panel->lcd_hbp - timmings->hor_sync_time) => (timmings->hor_back_porch + timmings->hor_sync_time - timmings->hor_sync_time) => timmings->hor_back_porch => mode->htotal - mode->hsync_end So, update the MIPI-DSI hbp value accordingly. Tested on 2-lane, 4-lane DSI LCD panels. Signed-off-by: Jagan Teki --- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index f6e3df8d2490..de0992052a90 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -482,7 +482,7 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi, */ #define HBP_PACKET_OVERHEAD6 hbp = max((unsigned int)HBP_PACKET_OVERHEAD, - (mode->hsync_start - mode->hdisplay) * Bpp - HBP_PACKET_OVERHEAD); + (mode->htotal - mode->hsync_end) * Bpp - HBP_PACKET_OVERHEAD); /* * The frontporch is set using a blanking packet (4 bytes + -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v4 12/26] drm/sun4i: sun6i_mipi_dsi: Fix DSI hblk timing calculation
hblk is adding line with all porch timing values, or timings values from htotal without sync time. Current driver is subtracting htotal with hsa, but the hsa is bounded with packet overhead. For real hblk calculation needed by subtracting htotal with back and front porch values and BSP code BPI-M64-bsp is eventually following the same. BPI-M64-bsp is computing hbp as (from linux-sunxi/ drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c) dsi_hblk = (ht-hspw)*dsi_pixel_bits[format]/8-(4+4+2); => (timmings->hor_total_time - timmings->hor_sync_time) => (mode->htotal - (mode->hsync_end - mode->hsync_start)) So, update the DSI hblk timing accordingly. Tested on 2-lane, 4-lane MIPI-DSI LCD panels. Signed-off-by: Jagan Teki --- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index de0992052a90..cd657ac4bdae 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -495,7 +495,7 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi, /* * hblk seems to be the line + porches length. */ - hblk = mode->htotal * Bpp - hsa; + hblk = (mode->htotal - (mode->hsync_end - mode->hsync_start)) * Bpp; /* * And I'm not entirely sure what vblk is about. The driver in -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v4 15/26] drm/sun4i: sun6i_mipi_dsi: Set proper vblk timing calculation
Unlike hblk, the vblk timings should follow an equation to compute
the desired value for lane 4 devices and rest of devices it would be 0.
BSP code from BPI-M64-bsp is computing vblk as for 4-lane devices
(from linux-sunxi
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
tmp = (ht*dsi_pixel_bits[format]/8)*vt-(4+dsi_hblk+2);
dsi_vblk = (lane-tmp%lane);
So, update the vblk timing calculation accordingly.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 32 --
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 63b924b89bd7..703722f7c81b 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -355,6 +355,30 @@ static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
SUN6I_DSI_INST_JUMP_CFG_NUM(1));
};
+static u16 sun6i_dsi_get_timings_vblk(struct sun6i_dsi *dsi,
+ struct drm_display_mode *mode, u16 hblk)
+{
+ struct mipi_dsi_device *device = dsi->device;
+ u16 vblk = 0;
+
+ /*
+* The vertical blank is set using a blanking packet (4 bytes +
+* payload + 2 bytes). Its minimal size is therefore 6 bytes
+*/
+#define VBLK_PACKET_OVERHEAD 6
+ if (device->lanes == 4) {
+ unsigned int Bpp;
+ int tmp;
+
+ Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
+ tmp = (mode->htotal * Bpp) * mode->vtotal -
+ (hblk + VBLK_PACKET_OVERHEAD);
+ vblk = (device->lanes - tmp % device->lanes);
+ }
+
+ return vblk;
+}
+
static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
struct drm_display_mode *mode)
{
@@ -503,13 +527,7 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
(mode->htotal - (mode->hsync_end - mode->hsync_start)) *
Bpp - HBLK_PACKET_OVERHEAD);
- /*
-* And I'm not entirely sure what vblk is about. The driver in
-* Allwinner BSP is using a rather convoluted calculation
-* there only for 4 lanes. However, using 0 (the !4 lanes
-* case) even with a 4 lanes screen seems to work...
-*/
- vblk = 0;
+ vblk = sun6i_dsi_get_timings_vblk(dsi, mode, hblk);
/* How many bytes do we need to send all payloads? */
bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk);
--
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[linux-sunxi] [PATCH v4 16/26] drm/sun4i: sun6i_mipi_dsi: Add support for VCC-DSI voltage regulator
Some boards have VCC-DSI pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
MIPI DSI driver.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 14 ++
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 3 +++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 703722f7c81b..2ea33db61ae1 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -1026,6 +1026,12 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
return PTR_ERR(base);
}
+ dsi->regulator = devm_regulator_get(dev, "vcc-dsi");
+ if (IS_ERR(dsi->regulator)) {
+ dev_err(dev, "Couldn't get VCC-DSI supply\n");
+ return PTR_ERR(dsi->regulator);
+ }
+
dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base,
_dsi_regmap_config);
if (IS_ERR(dsi->regs)) {
@@ -1107,6 +1113,13 @@ static int sun6i_dsi_remove(struct platform_device *pdev)
static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
{
struct sun6i_dsi *dsi = dev_get_drvdata(dev);
+ int err;
+
+ err = regulator_enable(dsi->regulator);
+ if (err) {
+ dev_err(dsi->dev, "failed to enable VCC-DSI supply: %d\n", err);
+ return err;
+ }
reset_control_deassert(dsi->reset);
if (dsi->variant->has_mod_clk)
@@ -1141,6 +1154,7 @@ static int __maybe_unused
sun6i_dsi_runtime_suspend(struct device *dev)
if (dsi->variant->has_mod_clk)
clk_disable_unprepare(dsi->mod_clk);
reset_control_assert(dsi->reset);
+ regulator_disable(dsi->regulator);
return 0;
}
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
index 597b62227019..0df60f84bab3 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
@@ -13,6 +13,8 @@
#include
#include
+#include
+
struct sun6i_dphy {
struct clk *bus_clk;
struct clk *mod_clk;
@@ -32,6 +34,7 @@ struct sun6i_dsi {
struct clk *bus_clk;
struct clk *mod_clk;
struct regmap *regs;
+ struct regulator*regulator;
struct reset_control*reset;
struct sun6i_dphy *dphy;
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 14/26] drm/sun4i: sun6i_mipi_dsi: Fix DSI hfp timing value
Current driver is calculating hfp maximum value by subtracting htotal with hsync_end which is front back value, but the hpp refers to front porch. Front porch value is calculating by subtracting hsync_start with hdisplay as per drm_mode timings, and BSP code from BPI-M64-bsp is eventually following the same. BPI-M64-bsp is computing hfp as (from linux-sunxi/ drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c) dsi_hbp = (hbp-hspw)*dsi_pixel_bits[format]/8 - (4+2); dsi_hact = x * dsi_pixel_bits[format]/8; dsi_hblk = (ht-hspw)*dsi_pixel_bits[format]/8-(4+4+2); dsi_hfp = dsi_hblk - (4+dsi_hact+2) - (4+dsi_hbp+2); Example, u32 fmt = dsi_pixel_bits[format]/8; => ((ht-hspw)*fmt - 10) - (6 + x * fmt) - (6 + (hbp-hspw)*fmt - 6) => (ht - hspw - x - (hbp - hspw)) * fmt - 16 => (ht - x - hbp) * fmt - 16 => (ht - x - (timmings->hor_total_time - timmings->hor_front_porch - x) * fmt - 16 => (timmings->hor_total_time - x - timmings->hor_total_time + timmings->hor_front_porch + x) * fmt - 16 => timmings->hor_front_porch * fmt - 16 So, update the DSI hfp timing accordingly. Tested on 2-lane, 4-lane MIPI-DSI LCD panels. Signed-off-by: Jagan Teki --- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index 1a3cdd5b72a0..63b924b89bd7 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -490,7 +490,8 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi, */ #define HFP_PACKET_OVERHEAD6 hfp = max((unsigned int)HFP_PACKET_OVERHEAD, - (mode->htotal - mode->hsync_end) * Bpp - HFP_PACKET_OVERHEAD); + (mode->hsync_start - mode->hdisplay) * Bpp - + HFP_PACKET_OVERHEAD); /* * hblk seems to be the line + porches length. -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v4 13/26] drm/sun4i: sun6i_mipi_dsi: Add DSI hblk packet overhead
Add 10 bytes packet overhead for hblk where blank is set using a blanking packet like (4 bytes + 4 bytes + payload + 2 bytes) This is according to BSP code from BPI-M64-bsp (from linux-sunxi/ drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c) dsi_hblk = (ht-hspw)*dsi_pixel_bits[format]/8-(4+4+2); So, add 10 bytes packet overhead for DSI hblk. Tested on 2-lane, 4-lane MIPI-DSI LCD panels. Signed-off-by: Jagan Teki --- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index cd657ac4bdae..1a3cdd5b72a0 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -494,8 +494,13 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi, /* * hblk seems to be the line + porches length. +* The blank is set using a blanking packet (4 bytes + 4 bytes + +* payload + 2 bytes). So minimal size is 10 bytes */ - hblk = (mode->htotal - (mode->hsync_end - mode->hsync_start)) * Bpp; +#define HBLK_PACKET_OVERHEAD 10 + hblk = max((unsigned int)HBLK_PACKET_OVERHEAD, + (mode->htotal - (mode->hsync_end - mode->hsync_start)) * + Bpp - HBLK_PACKET_OVERHEAD); /* * And I'm not entirely sure what vblk is about. The driver in -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v6 4/4] arm64: defconfig: Enable PWM_SUN4I
On Tue, Nov 13, 2018 at 05:45:35PM +0530, Jagan Teki wrote: > Allwinner PWM support need for ARM64 Allwinner SoC's > which used pwms, builds it as module. > > Signed-off-by: Jagan Teki Applied all 4 patches, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v4 03/26] clk: sunxi-ng: Add check for maximum rate to NKM PLLs
On Tue, Nov 13, 2018 at 04:46:10PM +0530, Jagan Teki wrote: > Some NKM PLLs, frequency can be set above PLL working range. > > Add a constraint for maximum supported rate. This way, drivers can > specify which is maximum allowed rate for PLL. > > Signed-off-by: Jagan Teki > Acked-by: Stephen Boyd As Vasily reported on a previous version, this should be squashed with the patch 2. > --- > drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++ > drivers/clk/sunxi-ng/ccu_nkm.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c > index 6b5ad990f802..b8b66cdd30bf 100644 > --- a/drivers/clk/sunxi-ng/ccu_nkm.c > +++ b/drivers/clk/sunxi-ng/ccu_nkm.c > @@ -128,6 +128,9 @@ static unsigned long ccu_nkm_round_rate(struct > ccu_mux_internal *mux, > if (rate < nkm->min_rate) > return nkm->min_rate; > > + if (nkm->max_rate && rate > nkm->max_rate) > + return nkm->max_rate; > + I would expect the test to be the same for the minimum and maximum cases. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v12 0/2] Initial Allwinner V3s CSI Support
Hi Yong, On Tue, Oct 30, 2018 at 04:09:48PM +0800, Yong Deng wrote: > I can't make v4l2-compliance always happy. > The V3s CSI support many pixformats. But they are not always available. > It's dependent on the input bus format (MEDIA_BUS_FMT_*). > Example: > V4L2_PIX_FMT_SBGGR8: MEDIA_BUS_FMT_SBGGR8_1X8 > V4L2_PIX_FMT_YUYV: MEDIA_BUS_FMT_YUYV8_2X8 > But I can't get the subdev's format code before starting stream as the > subdev may change it. So I can't know which pixformats are available. > So I exports all the pixformats supported by SoC. > The result is the app (v4l2-compliance) is likely to fail on streamon. > > This patchset add initial support for Allwinner V3s CSI. > > Allwinner V3s SoC features a CSI module with parallel interface. > > This patchset implement a v4l2 framework driver and add a binding > documentation for it. I've tested this version today, and I needed this patch to make it work on top of v4.20: http://code.bulix.org/9o8fw5-503690?raw Once that patch applied, my tests were working as expected. If that make sense, could you resubmit a new version with these merged so that we can try to target 4.21? Thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] [PATCH v6 3/4] arm64: defconfig: Enable DRM_SUN8I_DW_HDMI
Allwinner DesignWare HDMI is needed for HDMI support in ARM64 Allwinner SoC's, build it as module. Signed-off-by: Jagan Teki --- Changes for v6: - none Changes for v5: - Enable it on defconfig Changes for v4: - none Changes for v3: - skip SUN8I enablement, since it built statically for arm32 Changes for v2: - Enable for SUN8I arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7f271178d421..cb614bd70716 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -447,6 +447,7 @@ CONFIG_DRM_EXYNOS_MIC=y CONFIG_DRM_ROCKCHIP=m CONFIG_DRM_SUN4I=m CONFIG_DRM_SUN8I_MIXER=m +CONFIG_DRM_SUN8I_DW_HDMI=m CONFIG_ROCKCHIP_ANALOGIX_DP=y CONFIG_ROCKCHIP_CDN_DP=y CONFIG_ROCKCHIP_DW_HDMI=y -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v6 2/4] arm64: defconfig: Enable DRM_SUN8I_MIXER
Allwinner Display Engine 2.0 Mixer is need for ARM64 Allwinner SoC's, build it as module. Signed-off-by: Jagan Teki --- Changes for v6: - none Changes for v5: - Enable it on defconfig Changes for v4, v3: - none Changes for v2: - Enable for SUN8I arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4b3844480a77..7f271178d421 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -446,6 +446,7 @@ CONFIG_DRM_EXYNOS_HDMI=y CONFIG_DRM_EXYNOS_MIC=y CONFIG_DRM_ROCKCHIP=m CONFIG_DRM_SUN4I=m +CONFIG_DRM_SUN8I_MIXER=m CONFIG_ROCKCHIP_ANALOGIX_DP=y CONFIG_ROCKCHIP_CDN_DP=y CONFIG_ROCKCHIP_DW_HDMI=y -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v6 1/4] clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
Allwinner SoC like SUN8I and SUN50I has DE2 CCU so enable them as default. Signed-off-by: Jagan Teki --- Changes for v6: - droped "depends on" since the CCU select based on MACH defined. Changes for v5: - remove DRM dependency Changes for v4, v3: - none Changes for v2: - Enable for MACH_SUN8I drivers/clk/sunxi-ng/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 826674d090fd..abbd518833b5 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -63,6 +63,7 @@ config SUN8I_V3S_CCU config SUN8I_DE2_CCU bool "Support for the Allwinner SoCs DE2 CCU" + default MACH_SUN8I || (ARM64 && ARCH_SUNXI) config SUN8I_R40_CCU bool "Support for the Allwinner R40 CCU" -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v4 01/26] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
On Tue, Nov 13, 2018 at 04:46:08PM +0530, Jagan Teki wrote: > DSI DPHY gate bit on MIPI DSI clock register is bit 15 > not bit 30. > > Signed-off-by: Jagan Teki > Acked-by: Stephen Boyd Applied, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v2 2/2] arm64: dts: allwinner: a64: Add device node for Mali-400 GPU
On Tue, Nov 13, 2018 at 05:30:54PM +0530, Jagan Teki wrote: > Add support for Allwinner A64 has Mali-400MP2. > > All interrupt lines are mentioned in the manual so used the same. > Used 408MHz as assigned clock rate used by BSP, so used the same as > well. You're not using that frequency anywhere. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] [PATCH v4 06/26] dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI
The MIPI DSI controller on Allwinner A64 is similar to Allwinner A31 without support of DSI mod clock. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt index 6a6cf5de08b0..9fa6e7a758ad 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt @@ -12,6 +12,7 @@ The DSI Encoder generates the DSI signal from the TCON's. Required properties: - compatible: value must be one of: * allwinner,sun6i-a31-mipi-dsi +* allwinner,sun50i-a64-mipi-dsi - reg: base address and size of memory-mapped region - interrupts: interrupt associated to this IP - clocks: phandles to the clocks feeding the DSI encoder -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v4 03/26] clk: sunxi-ng: Add check for maximum rate to NKM PLLs
Some NKM PLLs, frequency can be set above PLL working range.
Add a constraint for maximum supported rate. This way, drivers can
specify which is maximum allowed rate for PLL.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++
drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 6b5ad990f802..b8b66cdd30bf 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -128,6 +128,9 @@ static unsigned long ccu_nkm_round_rate(struct
ccu_mux_internal *mux,
if (rate < nkm->min_rate)
return nkm->min_rate;
+ if (nkm->max_rate && rate > nkm->max_rate)
+ return nkm->max_rate;
+
ccu_nkm_find_best(*parent_rate, rate, &_nkm);
rate = *parent_rate * _nkm.n * _nkm.k / _nkm.m;
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
index ff5bd00f429f..c82590481188 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.h
+++ b/drivers/clk/sunxi-ng/ccu_nkm.h
@@ -36,6 +36,7 @@ struct ccu_nkm {
unsigned intfixed_post_div;
unsigned intmin_rate;
+ unsigned intmax_rate;
struct ccu_common common;
};
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 10/26] drm/sun4i: sun6i_mipi_dsi: Refactor vertical video start delay
Video start delay can be computed by subtracting total vertical
timing with front porch timing and with adding 1 delay line for TCON.
BSP code form BPI-M64-bsp is computing video start delay as
(from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
u32 vfp = panel->lcd_vt - panel->lcd_y - panel->lcd_vbp;
=> (panel->lcd_vt) - panel->lcd_y - (panel->lcd_vbp)
=> (timmings->ver_front_porch + panel->lcd_vbp + panel->lcd_y)
- panel->lcd_y - (panel->lcd_vbp)
=> timmings->ver_front_porch + panel->lcd_vbp + panel->lcd_y
- panel->lcd_y - panel->lcd_vbp
=> timmings->ver_front_porch
So, update the start delay computation accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index fc4252d96c38..f6e3df8d2490 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -358,7 +358,17 @@ static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
struct drm_display_mode *mode)
{
- return mode->vtotal - (mode->vsync_end - mode->vdisplay) + 1;
+ u32 vfp = mode->vsync_start - mode->vdisplay;
+ u32 start_delay;
+
+ start_delay = mode->vtotal - vfp + 1;
+ if (start_delay > mode->vtotal)
+ start_delay -= mode->vtotal;
+
+ if (!start_delay)
+ start_delay = 1;
+
+ return start_delay;
}
static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 08/26] drm/sun4i: sun6i_mipi_dsi: Fix VBP size calculation
The horizontal and vertical back porch calculation in BSP code is simply following the Linux drm comment diagram, in include/drm/drm_modes.h which is [hv]back porch = [hv]total - [hv]sync_end BSP code form BPI-M64-bsp is calculating vertical back porch as (from linux-sunxi/drivers/video/sunxi/disp2/disp/de/disp_lcd.c) timmings->ver_sync_time= panel_info->lcd_vspw; timmings->ver_back_porch= panel_info->lcd_vbp-panel_info->lcd_vspw; vbp = panel->lcd_vbp; vspw = panel->lcd_vspw; dsi_dev[sel]->dsi_basic_size0.bits.vbp = vbp-vspw; dsi_dev[sel]->dsi_basic_size0.bits.vbp = panel->lcd_vbp - panel->lcd_vspw; => timmings->ver_back_porch + panel_info->lcd_vspw - panel_info->lcd_vspw => timmings->ver_back_porch => mode->vtotal - mode->end Which evatually same as mode->vtotal - mode->vsync_end so update the same in SUN6I_DSI_BASIC_SIZE0_VBP On the information note, existing SUN6I_DSI_BASIC_SIZE0_VSA is proper value. Signed-off-by: Jagan Teki --- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index cdd44a1307b3..eeea977604ac 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -526,8 +526,8 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi, regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG, SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end - mode->vsync_start) | -SUN6I_DSI_BASIC_SIZE0_VBP(mode->vsync_start - - mode->vdisplay)); +SUN6I_DSI_BASIC_SIZE0_VBP(mode->vtotal - + mode->vsync_end)); regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG, SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) | -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v4 07/26] drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param transfer
Short transfer write support for DCS and Generic transfer types
share similar way to process command sequence in DSI block so
add generic write 2 param transfer type macro so-that the panels
which are requesting similar transfer type may process properly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 50f535ae57e9..cdd44a1307b3 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -871,6 +871,7 @@ static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host
*host,
switch (msg->type) {
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+ case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
ret = sun6i_dsi_dcs_write_short(dsi, msg);
break;
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 05/26] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
So, alter has_mod_clk bool via driver data for respective
SoC's compatible.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 561de393ea23..50f535ae57e9 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -1120,11 +1120,18 @@ static const struct sun6i_dsi_variant sun6i_a31_dsi = {
.has_mod_clk = true,
};
+static const struct sun6i_dsi_variant sun50i_a64_dsi = {
+};
+
static const struct of_device_id sun6i_dsi_of_table[] = {
{
.compatible = "allwinner,sun6i-a31-mipi-dsi",
.data = _a31_dsi,
},
+ {
+ .compatible = "allwinner,sun50i-a64-mipi-dsi",
+ .data = _a64_dsi,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 02/26] clk: sunxi-ng: Add check for minimal rate to NKM PLLs
Some NKM PLLs doesn't work well when their output clock rate is set below
certain rate.
So, add support for minimal rate for relevant PLLs.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++
drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 841840e35e61..6b5ad990f802 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -125,6 +125,9 @@ static unsigned long ccu_nkm_round_rate(struct
ccu_mux_internal *mux,
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nkm->fixed_post_div;
+ if (rate < nkm->min_rate)
+ return nkm->min_rate;
+
ccu_nkm_find_best(*parent_rate, rate, &_nkm);
rate = *parent_rate * _nkm.n * _nkm.k / _nkm.m;
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
index cc6efb70a102..ff5bd00f429f 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.h
+++ b/drivers/clk/sunxi-ng/ccu_nkm.h
@@ -35,6 +35,7 @@ struct ccu_nkm {
struct ccu_mux_internal mux;
unsigned intfixed_post_div;
+ unsigned intmin_rate;
struct ccu_common common;
};
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 01/26] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index f7d297368eb2..019d67bf97c4 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -581,7 +581,7 @@ static const char * const dsi_dphy_parents[] = {
"pll-video0", "pll-periph0" };
static const u8 dsi_dphy_table[] = { 0, 2, };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
dsi_dphy_parents, dsi_dphy_table,
- 0x168, 0, 4, 8, 2, BIT(31),
CLK_SET_RATE_PARENT);
+ 0x168, 0, 4, 8, 2, BIT(15),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v4 00/26] drm/sun4i: Allwinner A64 MIPI-DSI support
This series fixed the issues related to work DSI on 2-lane panel which is reported on previous version[1]. This supposed to be a clean series, where it support Allwinner A64 MIPI-DSI support for 4-lane, 2-lane DSI panels. This series fixed all previous series comments along with checkpatch warnings/error. Changes for v4: - droppoed untested CCU_FEATURE_FIXED_POSTDIV check code in nkm min, max rate patches - create two patches for "Add Allwinner A64 MIPI DSI support" one for has_mod_clk quirk and other one for A64 support - use existing driver code construct for hblk computation - dropped "Increase hfp packet overhead" patch [2], though BSP added this but we have no issues as of now. (no issues on panel side w/o this change) - create separate function for vblk computation - enable vcc-dsi regulator in dsi_runtime_resume - collect Rob, Acked-by - update MAINTAINERS file for panel drivers - cleanup commit messages - fixed checkpatch warnings/errors [2] https://patchwork.kernel.org/patch/10657541/ [1] https://patchwork.kernel.org/patch/10657619/ Jagan Teki (26): clk: sunxi-ng: a64: Fix gate bit of DSI DPHY clk: sunxi-ng: Add check for minimal rate to NKM PLLs clk: sunxi-ng: Add check for maximum rate to NKM PLLs drm/sun4i: sun6i_mipi_dsi: Add has_mod_clk quirk drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param transfer drm/sun4i: sun6i_mipi_dsi: Fix VBP size calculation drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits drm/sun4i: sun6i_mipi_dsi: Refactor vertical video start delay drm/sun4i: sun6i_mipi_dsi: Fix DSI hbp timing value drm/sun4i: sun6i_mipi_dsi: Fix DSI hblk timing calculation drm/sun4i: sun6i_mipi_dsi: Add DSI hblk packet overhead drm/sun4i: sun6i_mipi_dsi: Fix DSI hfp timing value drm/sun4i: sun6i_mipi_dsi: Set proper vblk timing calculation drm/sun4i: sun6i_mipi_dsi: Add support for VCC-DSI voltage regulator dt-bindings: sun6i-dsi: Add VCC-DSI supply property dt-bindings: panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge drm/panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge dt-bindings: panel: Add Techstar TS8550B MIPI-DSI panel drm/panel: Add Techstar TS8550B MIPI-DSI LCD panel clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI dt-bindings: sun6i-dsi: Add compatible for A64 DPHY arm64: dts: allwinner: a64: Add DSI pipeline [DO NOT MERGE] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel arm64: dts: allwinner: a64-amarula-relic: Enable Techstar TS8550B MIPI-DSI panel .../display/panel/bananapi,s070wv20-ct16.txt | 31 +- .../display/panel/techstar,ts8550b.txt| 22 ++ .../bindings/display/sunxi/sun6i-dsi.txt | 5 + MAINTAINERS | 12 + .../allwinner/sun50i-a64-amarula-relic.dts| 46 +++ .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 42 +++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45 +++ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 4 +- drivers/clk/sunxi-ng/ccu_nkm.c| 6 + drivers/clk/sunxi-ng/ccu_nkm.h| 2 + drivers/gpu/drm/panel/Kconfig | 18 + drivers/gpu/drm/panel/Makefile| 2 + .../panel/panel-bananapi-s070wv20-icn6211.c | 298 .../gpu/drm/panel/panel-techstar-ts8550b.c| 324 ++ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c| 125 +-- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h| 8 + 16 files changed, 961 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/techstar,ts8550b.txt create mode 100644 drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c create mode 100644 drivers/gpu/drm/panel/panel-techstar-ts8550b.c -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v2 1/2] dt-bindings: gpu: mali-utgard: Add compatible for A64 Mali
On Tue, Nov 13, 2018 at 05:30:53PM +0530, Jagan Teki wrote: > Allwinner A64 has Mali-400MP2, so document the relevant compatible > as "allwinner,sun50i-a64-mali" > > Signed-off-by: Jagan Teki > --- > Changes for v2: > - New patch, separated from previous version patch. > > Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > index 63cd91176a68..a0ee62a5b221 100644 > --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > @@ -11,6 +11,7 @@ Required properties: >+ allwinner,sun4i-a10-mali >+ allwinner,sun7i-a20-mali >+ allwinner,sun8i-h3-mali > + + allwinner,sun50i-a64-mali It uses a reset property, so that must be documented as well later in that file. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] [PATCH v2 2/2] arm64: dts: allwinner: a64: Add device node for Mali-400 GPU
Add support for Allwinner A64 has Mali-400MP2.
All interrupt lines are mentioned in the manual so used the same.
Used 408MHz as assigned clock rate used by BSP, so used the same as
well.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Drop assigned clock properties
- Separate dt-bindings as separate patch.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 +++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d6f269883759..d507be9879d8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -813,6 +813,28 @@
};
};
+ mali: gpu@1c4 {
+ compatible = "allwinner,sun50i-a64-mali",
"arm,mali-400";
+ reg = <0x01c4 0x1>;
+ interrupts = ,
+,
+,
+,
+,
+,
+;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = < CLK_BUS_GPU>, < CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = < RST_BUS_GPU>;
+ };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v2 1/2] dt-bindings: gpu: mali-utgard: Add compatible for A64 Mali
Allwinner A64 has Mali-400MP2, so document the relevant compatible as "allwinner,sun50i-a64-mali" Signed-off-by: Jagan Teki --- Changes for v2: - New patch, separated from previous version patch. Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 63cd91176a68..a0ee62a5b221 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -11,6 +11,7 @@ Required properties: + allwinner,sun4i-a10-mali + allwinner,sun7i-a20-mali + allwinner,sun8i-h3-mali + + allwinner,sun50i-a64-mali + allwinner,sun50i-h5-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v4 25/26] [DO NOT MERGE] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel
On Tue, 13 Nov 2018 16:46:32 +0530
Jagan Teki wrote:
Hi,
> This patch add support for Bananapi S070WV20-CT16 DSI panel to
> BPI-M64 board.
>
> DSI panel connected via board DSI port with,
> - DC1SW as AVDD supply
Are you sure of that? I don't see anything in the schematic to support
this. The only power lines that go to the DSI connector are DCDC1 and
PS. DC1SW is only connected to PortD on the SoC and to the Ethernet PHY.
Is there anything I miss?
> - DCDC1 as DVDD supply
That seems right, but doesn't match with what you write below.
> - PD6 gpio for reset pin
> - PD5 gpio for backlight enable pin
> - PD7 gpio for backlight vdd supply
>
> Signed-off-by: Jagan Teki
> ---
> .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 42
> +++ 1 file changed, 42 insertions(+)
>
> diff --git
> a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index
> ef1c90401bb2..6cb010e3bbd9 100644 ---
> a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++
> b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -45,6
> +45,7 @@ #include "sun50i-a64.dtsi"
> #include
> +#include
>
> / {
> model = "BananaPi-M64";
> @@ -56,6 +57,15 @@
> serial1 =
> };
>
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <_pwm 0 5 PWM_POLARITY_INVERTED>;
> + brightness-levels = <1 2 4 8 16 32 64 128 512>;
> + default-brightness-level = <2>;
> + enable-gpios = < 3 5 GPIO_ACTIVE_HIGH>; /*
> LCD-BL-EN: PD5 */
> + power-supply = <_vdd_backlight>;
> + };
> +
> chosen {
> stdout-path = "serial0:115200n8";
> };
> @@ -91,6 +101,15 @@
> };
> };
>
> + reg_vdd_backlight: vdd-backlight {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd-backlight";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + gpio = < 3 7 GPIO_ACTIVE_HIGH>; /* LCD-PWR-EN:
> PD7 */
> + enable-active-high;
> + };
> +
> wifi_pwrseq: wifi_pwrseq {
> compatible = "mmc-pwrseq-simple";
> reset-gpios = <_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
> @@ -101,6 +120,23 @@
> status = "okay";
> };
>
> + {
> + status = "okay";
> +};
> +
> + {
> + status = "okay";
> +
> + panel@0 {
> + compatible = "bananapi,s070wv20-ct16-icn6211";
> + reg = <0>;
> + avdd-supply = <_dc1sw>;
As mentioned above, I don't see this on the DSI connector.
> + dvdd-supply = <_dldo1>;
Mmh, this line is connected to the *SoC*, to drive the DSI data lines
or the DPHY, presumably. So I wouldn't expect it in the panel node, but
rather in the DPHY or DSI node. Although I can't find a power-supply
property in those bindings.
Cheers,
Andre.
> + reset-gpios = < 3 6 GPIO_ACTIVE_HIGH>; /*
> LCD-RST: PD6 */
> + backlight = <>;
> + };
> +};
> +
> {
> status = "okay";
> };
> @@ -193,6 +229,12 @@
> status = "okay";
> };
>
> +_pwm {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pwm_pin>;
> + status = "okay";
> +};
> +
> _rsb {
> status = "okay";
>
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[linux-sunxi] Re: [PATCH v4 26/26] arm64: dts: allwinner: a64-amarula-relic: Enable Techstar TS8550B MIPI-DSI panel
On Tue, 13 Nov 2018 16:46:33 +0530
Jagan Teki wrote:
Hi,
I couldn't find a schematic for this board, but some things in here
look inconsistent:
> Amarula A64-Relic board by default bound with Techstar TS8550B
> MIPI-DSI panel, add support for it.
>
> DSI panel connected via board DSI port with,
> - DC1SW as AVDD supply
> - DCDC2 as DVDD supply
Are you sure of that? That's typically the CPU power supply. Also I
can't find it below. Should that read DLDO2 instead?
> - DCDC1 as VCC-DSI supply
Can't find this below, either. Is it DLDO1?
> - PD24 gpio for reset pin
> - PD23 gpio for backlight enable pin
>
> Signed-off-by: Jagan Teki
> ---
> .../allwinner/sun50i-a64-amarula-relic.dts| 46
> +++ 1 file changed, 46 insertions(+)
>
> diff --git
> a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts index
> 6cb2b7f0c817..ecc0d8094815 100644 ---
> a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts +++
> b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts @@ -9,6
> +9,7 @@ #include "sun50i-a64.dtsi"
> #include
> +#include
>
> / {
> model = "Amarula A64-Relic";
> @@ -18,6 +19,14 @@
> serial0 =
> };
>
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = < 0 5 PWM_POLARITY_INVERTED>;
> + brightness-levels = <1 2 4 8 16 32 64 128 512>;
> + default-brightness-level = <2>;
> + enable-gpios = < 3 23 GPIO_ACTIVE_HIGH>; /*
> LCD-BL-EN: PD23 */
> + };
> +
> chosen {
> stdout-path = "serial0:115200n8";
> };
> @@ -30,6 +39,28 @@
> };
> };
>
> + {
> + status = "okay";
> +};
> +
> + {
> + status = "okay";
> +};
> +
> + {
> + vcc-dsi-supply = <_dldo1>;
Ah, there we have the SoC DSI power supply I was missing for the
BPi-M64 patch.
But is it DLDO1 or DCDC1, like you wrote above?
> + status = "okay";
> +
> + panel@0 {
> + compatible = "techstar,ts8550b";
> + reg = <0>;
> + avdd-supply = <_dc1sw>;
> + dvdd-supply = <_dldo2>;
> + reset-gpios = < 3 24 GPIO_ACTIVE_HIGH>; /*
> LCD-RST: PD24 */
> + backlight = <>;
> + };
> +};
> +
> {
> status = "okay";
> };
> @@ -72,6 +103,12 @@
> status = "okay";
> };
>
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pin>;
> + status = "okay";
> +};
> +
> _rsb {
> status = "okay";
>
> @@ -107,6 +144,15 @@
> regulator-name = "vcc-pll-avcc";
> };
>
> +_dc1sw {
> + /*
> + * This regulator also indirectly drives the PD pingroup
> GPIOs,
> + * which also controls the power LED.
> + */
Is that true for this board as well or is this just a copy
leftover from the BananaPi-M64? If not, you should loose the
regulator-always-on property.
> + regulator-always-on;
> + regulator-name = "vcc-phy";
Shouldn't this be called "vcc-dsi" or so?
Cheers,
Andre.
> +};
> +
> _dcdc1 {
> regulator-always-on;
> regulator-min-microvolt = <330>;
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[linux-sunxi] [PATCH v3 1/2] dt-bindings: gpu: mali-utgard: Add compatible for A64 Mali
Allwinner A64 has Mali-400MP2, so document the relevant compatible as "allwinner,sun50i-a64-mali" along with reset line. Signed-off-by: Jagan Teki --- Changes for v3: - document reset line Changes for v2: - New patch, separated from previous version patch. Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 63cd91176a68..3f128e4f95c6 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -11,6 +11,7 @@ Required properties: + allwinner,sun4i-a10-mali + allwinner,sun7i-a20-mali + allwinner,sun8i-h3-mali + + allwinner,sun50i-a64-mali + allwinner,sun50i-h5-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali @@ -73,6 +74,10 @@ to specify one more vendor-specific compatible, among: Required properties: * resets: phandle to the reset line for the GPU + - allwinner,sun50i-a64-mali +Required properties: + * resets: phandle to the reset line for the GPU + - allwinner,sun50i-h5-mali Required properties: * resets: phandle to the reset line for the GPU -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v3 2/2] arm64: dts: allwinner: a64: Add device node for Mali-400 GPU
Add support for Allwinner A64 has Mali-400MP2.
All interrupt lines are mentioned in the manual so used the same.
Signed-off-by: Jagan Teki
---
Changes for v3:
- Clean commit message
Changes for v2:
- Drop assigned clock properties
- Separate dt-bindings as separate patch.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 +++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d6f269883759..d507be9879d8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -813,6 +813,28 @@
};
};
+ mali: gpu@1c4 {
+ compatible = "allwinner,sun50i-a64-mali",
"arm,mali-400";
+ reg = <0x01c4 0x1>;
+ interrupts = ,
+,
+,
+,
+,
+,
+;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = < CLK_BUS_GPU>, < CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = < RST_BUS_GPU>;
+ };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] Re: [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY
在 2018-10-18四的 08:58 -0500，Rob Herring写道： > On Sat, Oct 13, 2018 at 9:42 PM Icenowy Zheng > wrote: > > > > 在 2018-10-05五的 15:58 -0500，Rob Herring写道： > > > On Thu, Oct 04, 2018 at 08:28:52PM +0800, Icenowy Zheng wrote: > > > > The new Allwinner H6 SoC contains a USB3 PHY that is wired to > > > > the > > > > external USB3 pins of the SoC. > > > > > > > > Add a device tree binding for the PHY. > > > > > > > > Signed-off-by: Icenowy Zheng > > > > Reviewed-by: Chen-Yu Tsai > > > > --- > > > > Changes in v4: > > > > - Changed Vbus regulator property to vbus-supply. > > > > > > > > Changes in v3: > > > > - Added Chen-Yu's Review tag. > > > > > > > > No changes in v2, v1. > > > > > > > > .../bindings/phy/sun50i-usb3-phy.txt | 23 > > > > +++ > > > > 1 file changed, 23 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/phy/sun50i- > > > > usb3-phy.txt > > > > > > > > diff --git a/Documentation/devicetree/bindings/phy/sun50i-usb3- > > > > phy.txt b/Documentation/devicetree/bindings/phy/sun50i-usb3- > > > > phy.txt > > > > new file mode 100644 > > > > index ..9f49c6b8c7e7 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt > > > > @@ -0,0 +1,23 @@ > > > > +Allwinner sun50i USB3 PHY > > > > +--- > > > > + > > > > +Required properties: > > > > +- compatible : should be one of > > > > + * allwinner,sun60i-h6-usb3-phy > > > > +- reg : a list of offset + length pairs > > > > +- #phy-cells : from the generic phy bindings, must be 0 > > > > +- clocks : phandle + clock specifier for the phy clock > > > > +- resets : phandle + reset specifier for the phy reset > > > > + > > > > +Optional Properties: > > > > +- vbus-supply : a phandle to a regulator that provides power > > > > to > > > > VBUS. > > > > > > This belongs in a connector node as it is part of the connector > > > unless > > > the phy physically needs Vbus for power. > > > > > > But others have done this, so all the phys can just be wrong... > > > > How should we reference the connector? > > > > Via OF graph or simply a property in PHY node? > > The connector is either a child of the controller or an OF graph from > the controller to the connector. The phy driver needs the controller > node and then it can walk the tree or graph to get the connector > node. By reading the binding, it says the connector should be a child of the "interface controller", not the USB controller. In this case I think the interface controller is the PHY rather than the USB controller. In addition, the connector is a passive component, and power management should be done by the "interface controller", either directly by the PHY or make a dummy interface controller driver that only controls the Vbus. > > Rob > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 01/15] dt-bindings: net: broadcom-bluetooth: Fix external clock names
On Tue, Nov 13, 2018 at 7:37 AM Rob Herring wrote: > > On Wed, Nov 07, 2018 at 06:12:54PM +0800, Chen-Yu Tsai wrote: > > The Broadcom Bluetooth controllers can take up to two external clocks: > > an external frequency reference, substituting the main crystal, and a > > LPO clock at 32.768 kHz substituting the internal LPO clock. > > > > In particular, the external LPO clock must be used when the controller > > does not have NVRAM connected, and the main reference frequency is not > > the default 20 MHz. This is described in detail in the datasheet. > > > > The original "extclk" clock name is ambiguous as to which of these it > > refers to, and some designs might even require both. > > > > This patch deprecates the existing name, and adds "txco" and "lpo". > > > > Signed-off-by: Chen-Yu Tsai > > --- > > Documentation/devicetree/bindings/net/broadcom-bluetooth.txt | 5 - > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt > > b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt > > index 4194ff7e6ee6..2535e54219af 100644 > > --- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt > > +++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt > > @@ -18,7 +18,10 @@ Optional properties: > > - shutdown-gpios: GPIO specifier, used to enable the BT module > > - device-wakeup-gpios: GPIO specifier, used to wakeup the controller > > - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor > > - - clocks: clock specifier if external clock provided to the controller > > + - clocks and clock-names: clock specifier if external clocks are provided > > + - "txco": external reference clock > > + - "extclk": deprecated, replaced by "txco" > > + - "lpo": external low power 32.768 kHz clock > > - clock-names: should be "extclk" > > This line should change? Yes. Missed that. > > 'clocks' needs to describe how many clocks and the order of them. > > 'clock-names' needs to list the names. Keep them separate. I was under the impression that when clock-names was used, the order of clocks shouldn't matter. Also, both clocks are optional. The controller can use a standalone crystal instead of an external TXCO, which would not get described in the device tree, and/or not use an LPO clock. How would one describe a device that has an LPO clock input but not a TXCO clock input? Last, IMHO listing them with name + description, one item per line is more readable then having the items on one line, then having the next line list all their respective names. If ordering and number of items is important, I could add the requirements to the description of "clocks and clock-names"? Thanks ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v4 08/10] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
在 2018-10-04四的 20:28 +0800，Icenowy Zheng写道：
> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> controlled).
>
> Add a driver for it.
>
> The register operations in this driver is mainly extracted from the
> BSP
> USB3 driver.
>
> Signed-off-by: Icenowy Zheng
> Reviewed-by: Chen-Yu Tsai
Kishon, I see this patch is picked to linux-next, however this patch is
not in the stage that can be picked, because for the Vbus of USB3 PHY
Rob Herring still have some problems.
Could you remove PATCH 7 and 8 in this patchset now?
Thanks!
> ---
> Changes in v4:
> - Added support for vbus-supply property.
>
> Changes in v3:
> - Dropped USB_SUPPORT dependency.
> - Added Chen-Yu's Review tag.
>
> No changes in v2, v1.
>
> drivers/phy/allwinner/Kconfig | 12 ++
> drivers/phy/allwinner/Makefile | 1 +
> drivers/phy/allwinner/phy-sun50i-usb3.c | 239
>
> 3 files changed, 252 insertions(+)
> create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c
>
> diff --git a/drivers/phy/allwinner/Kconfig
> b/drivers/phy/allwinner/Kconfig
> index cdc1e745ba47..064096e6a4e5 100644
> --- a/drivers/phy/allwinner/Kconfig
> +++ b/drivers/phy/allwinner/Kconfig
> @@ -29,3 +29,15 @@ config PHY_SUN9I_USB
> sun9i SoCs.
>
> This driver controls each individual USB 2 host PHY.
> +
> +config PHY_SUN50I_USB3
> + tristate "Allwinner sun50i SoC USB3 PHY driver"
> + depends on ARCH_SUNXI && HAS_IOMEM && OF
> + depends on RESET_CONTROLLER
> + select USB_COMMON
> + select GENERIC_PHY
> + help
> + Enable this to support the USB3.0-capable transceiver that is
> + part of some Allwinner sun50i SoCs.
> +
> + This driver controls each individual USB 2+3 host PHY combo.
> diff --git a/drivers/phy/allwinner/Makefile
> b/drivers/phy/allwinner/Makefile
> index 8605529c01a1..a8d01e9073c2 100644
> --- a/drivers/phy/allwinner/Makefile
> +++ b/drivers/phy/allwinner/Makefile
> @@ -1,2 +1,3 @@
> obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
> obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o
> +obj-$(CONFIG_PHY_SUN50I_USB3)+= phy-sun50i-usb3.o
> diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c
> b/drivers/phy/allwinner/phy-sun50i-usb3.c
> new file mode 100644
> index ..70c299c01c3e
> --- /dev/null
> +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
> @@ -0,0 +1,239 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Allwinner sun50i(H6) USB 3.0 phy driver
> + *
> + * Copyright (C) 2017 Icenowy Zheng
> + *
> + * Based on phy-sun9i-usb.c, which is:
> + *
> + * Copyright (C) 2014-2015 Chen-Yu Tsai
> + *
> + * Based on code from Allwinner BSP, which is:
> + *
> + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* Interface Status and Control Registers */
> +#define SUNXI_ISCR 0x00
> +#define SUNXI_PIPE_CLOCK_CONTROL 0x14
> +#define SUNXI_PHY_TUNE_LOW 0x18
> +#define SUNXI_PHY_TUNE_HIGH 0x1c
> +#define SUNXI_PHY_EXTERNAL_CONTROL 0x20
> +
> +/* USB2.0 Interface Status and Control Register */
> +#define SUNXI_ISCR_FORCE_VBUS(3 << 12)
> +
> +/* PIPE Clock Control Register */
> +#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6)
> +
> +/* PHY External Control Register */
> +#define SUNXI_PEC_EXTERN_VBUS(3 << 1)
> +#define SUNXI_PEC_SSC_EN (1 << 24)
> +#define SUNXI_PEC_REF_SSP_EN (1 << 26)
> +
> +/* PHY Tune High Register */
> +#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19)
> +#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19)
> +#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13)
> +#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13)
> +#define SUNXI_TX_SWING_FULL(n) ((n) << 6)
> +#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6)
> +#define SUNXI_LOS_BIAS(n)((n) << 3)
> +#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
> +#define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
> +#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2)
> +
> +struct sun50i_usb3_phy {
> + struct phy *phy;
> + void __iomem *regs;
> + struct reset_control *reset;
> + struct clk *clk;
> + bool regulator_on;
> + struct regulator *vbus;
> +};
> +
> +static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
> +{
> + u32 val;
> +
> + val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
> + val |= SUNXI_PEC_EXTERN_VBUS;
> + val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
> + writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
> +
> + val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
> + val |= SUNXI_PCC_PIPE_CLK_OPEN;
> + writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
> +
> + val = readl(phy->regs + SUNXI_ISCR);
> + val |= SUNXI_ISCR_FORCE_VBUS;
> + writel(val, phy->regs
[linux-sunxi] Re: [PATCH v4 25/26] [DO NOT MERGE] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel
On Tue, Nov 13, 2018 at 5:52 PM Andre Przywara wrote:
>
> On Tue, 13 Nov 2018 16:46:32 +0530
> Jagan Teki wrote:
>
> Hi,
>
> > This patch add support for Bananapi S070WV20-CT16 DSI panel to
> > BPI-M64 board.
> >
> > DSI panel connected via board DSI port with,
> > - DC1SW as AVDD supply
>
> Are you sure of that? I don't see anything in the schematic to support
> this. The only power lines that go to the DSI connector are DCDC1 and
> PS. DC1SW is only connected to PortD on the SoC and to the Ethernet PHY.
> Is there anything I miss?
Thanks for the comment, yes dc1sw is connected in ephy. I have reused
dc1, BSP is attached lcd_power1 to axp81x_dc1sw [1]. I just looking
for someone to comment, may be we can skip this regulator attachment.
>
> > - DCDC1 as DVDD supply
>
> That seems right, but doesn't match with what you write below.
Commit need to fix s/DCDC1/DLDO1
>
> > - PD6 gpio for reset pin
> > - PD5 gpio for backlight enable pin
> > - PD7 gpio for backlight vdd supply
> >
> > Signed-off-by: Jagan Teki
> > ---
> > .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 42
> > +++ 1 file changed, 42 insertions(+)
> >
> > diff --git
> > a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
> > b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index
> > ef1c90401bb2..6cb010e3bbd9 100644 ---
> > a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++
> > b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -45,6
> > +45,7 @@ #include "sun50i-a64.dtsi"
> > #include
> > +#include
> >
> > / {
> > model = "BananaPi-M64";
> > @@ -56,6 +57,15 @@
> > serial1 =
> > };
> >
> > + backlight: backlight {
> > + compatible = "pwm-backlight";
> > + pwms = <_pwm 0 5 PWM_POLARITY_INVERTED>;
> > + brightness-levels = <1 2 4 8 16 32 64 128 512>;
> > + default-brightness-level = <2>;
> > + enable-gpios = < 3 5 GPIO_ACTIVE_HIGH>; /*
> > LCD-BL-EN: PD5 */
> > + power-supply = <_vdd_backlight>;
> > + };
> > +
> > chosen {
> > stdout-path = "serial0:115200n8";
> > };
> > @@ -91,6 +101,15 @@
> > };
> > };
> >
> > + reg_vdd_backlight: vdd-backlight {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vdd-backlight";
> > + regulator-min-microvolt = <330>;
> > + regulator-max-microvolt = <330>;
> > + gpio = < 3 7 GPIO_ACTIVE_HIGH>; /* LCD-PWR-EN:
> > PD7 */
> > + enable-active-high;
> > + };
> > +
> > wifi_pwrseq: wifi_pwrseq {
> > compatible = "mmc-pwrseq-simple";
> > reset-gpios = <_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
> > @@ -101,6 +120,23 @@
> > status = "okay";
> > };
> >
> > + {
> > + status = "okay";
> > +};
> > +
> > + {
> > + status = "okay";
> > +
> > + panel@0 {
> > + compatible = "bananapi,s070wv20-ct16-icn6211";
> > + reg = <0>;
> > + avdd-supply = <_dc1sw>;
>
> As mentioned above, I don't see this on the DSI connector.
>
> > + dvdd-supply = <_dldo1>;
>
> Mmh, this line is connected to the *SoC*, to drive the DSI data lines
> or the DPHY, presumably. So I wouldn't expect it in the panel node, but
> rather in the DPHY or DSI node. Although I can't find a power-supply
> property in those bindings.
Got it, this has to attach via vcc-dsi-supply.
[1]
https://github.com/BPI-SINOVOIP/BPI-M64-bsp/blob/master/bootloader/blobs/bpi-m64-lcd7.dts#L2266
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[linux-sunxi] Re: [PATCH v4 25/26] [DO NOT MERGE] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel
On Wed, Nov 14, 2018 at 2:31 PM Jagan Teki wrote:
>
> On Tue, Nov 13, 2018 at 5:52 PM Andre Przywara wrote:
> >
> > On Tue, 13 Nov 2018 16:46:32 +0530
> > Jagan Teki wrote:
> >
> > Hi,
> >
> > > This patch add support for Bananapi S070WV20-CT16 DSI panel to
> > > BPI-M64 board.
> > >
> > > DSI panel connected via board DSI port with,
> > > - DC1SW as AVDD supply
> >
> > Are you sure of that? I don't see anything in the schematic to support
> > this. The only power lines that go to the DSI connector are DCDC1 and
> > PS. DC1SW is only connected to PortD on the SoC and to the Ethernet PHY.
> > Is there anything I miss?
>
> Thanks for the comment, yes dc1sw is connected in ephy. I have reused
> dc1, BSP is attached lcd_power1 to axp81x_dc1sw [1]. I just looking
> for someone to comment, may be we can skip this regulator attachment.
That seems sketchy. The schematics show the connector has feeds from both
the unregulated output IPSOUT (PS) and DCDC1. For designs with RGB LCD
panels, we only see the PS feed. Since the LCD panel can be used in either
RGB or MIPI DSI mode, I highly suspect the DCDC1 supply feeds the bridge
IC.
As for DC1SW, this is likely referenced because it provides power to the
GPIO lines that are used to control the LCD panel. If you don't provide
power, you can't pull them up.
While many of us dislike FEX and the new FEX-derived device tree, they
do provide some information, such as regulator usage. Note that each
regulator output has multiple names, which likely denote specific
usages.
I've asked BPI for schematics on the bridge board. Hopefully we'll
have something in more detail. In the meantime, I suggest leaving
this panel out of your next submission, and focus on getting the bulk
of the dsi driver and dts changes in first.
ChenYu
>
> >
> > > - DCDC1 as DVDD supply
> >
> > That seems right, but doesn't match with what you write below.
>
> Commit need to fix s/DCDC1/DLDO1
>
> >
> > > - PD6 gpio for reset pin
> > > - PD5 gpio for backlight enable pin
> > > - PD7 gpio for backlight vdd supply
> > >
> > > Signed-off-by: Jagan Teki
> > > ---
> > > .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 42
> > > +++ 1 file changed, 42 insertions(+)
> > >
> > > diff --git
> > > a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
> > > b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index
> > > ef1c90401bb2..6cb010e3bbd9 100644 ---
> > > a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++
> > > b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -45,6
> > > +45,7 @@ #include "sun50i-a64.dtsi"
> > > #include
> > > +#include
> > >
> > > / {
> > > model = "BananaPi-M64";
> > > @@ -56,6 +57,15 @@
> > > serial1 =
> > > };
> > >
> > > + backlight: backlight {
> > > + compatible = "pwm-backlight";
> > > + pwms = <_pwm 0 5 PWM_POLARITY_INVERTED>;
> > > + brightness-levels = <1 2 4 8 16 32 64 128 512>;
> > > + default-brightness-level = <2>;
> > > + enable-gpios = < 3 5 GPIO_ACTIVE_HIGH>; /*
> > > LCD-BL-EN: PD5 */
> > > + power-supply = <_vdd_backlight>;
> > > + };
> > > +
> > > chosen {
> > > stdout-path = "serial0:115200n8";
> > > };
> > > @@ -91,6 +101,15 @@
> > > };
> > > };
> > >
> > > + reg_vdd_backlight: vdd-backlight {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "vdd-backlight";
> > > + regulator-min-microvolt = <330>;
> > > + regulator-max-microvolt = <330>;
> > > + gpio = < 3 7 GPIO_ACTIVE_HIGH>; /* LCD-PWR-EN:
> > > PD7 */
> > > + enable-active-high;
> > > + };
> > > +
> > > wifi_pwrseq: wifi_pwrseq {
> > > compatible = "mmc-pwrseq-simple";
> > > reset-gpios = <_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
> > > @@ -101,6 +120,23 @@
> > > status = "okay";
> > > };
> > >
> > > + {
> > > + status = "okay";
> > > +};
> > > +
> > > + {
> > > + status = "okay";
> > > +
> > > + panel@0 {
> > > + compatible = "bananapi,s070wv20-ct16-icn6211";
> > > + reg = <0>;
> > > + avdd-supply = <_dc1sw>;
> >
> > As mentioned above, I don't see this on the DSI connector.
> >
> > > + dvdd-supply = <_dldo1>;
> >
> > Mmh, this line is connected to the *SoC*, to drive the DSI data lines
> > or the DPHY, presumably. So I wouldn't expect it in the panel node, but
> > rather in the DPHY or DSI node. Although I can't find a power-supply
> > property in those bindings.
>
> Got it, this has to attach via vcc-dsi-supply.
>
> [1]
> https://github.com/BPI-SINOVOIP/BPI-M64-bsp/blob/master/bootloader/blobs/bpi-m64-lcd7.dts#L2266
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[linux-sunxi] Re: [PATCH 14/15] ARM: dts: sunxi: Enable Broadcom-based Bluetooth for multiple boards
On Thu, Nov 8, 2018 at 4:24 PM Maxime Ripard wrote:
>
> On Wed, Nov 07, 2018 at 06:13:07PM +0800, Chen-Yu Tsai wrote:
> > This patch adds the Bluetooth node, and the underlying UART node if it's
> > missing, to the board device tree file for several boards. The LPO clock
> > is also added to the WiFi side's power sequencing node if it's missing,
> > to correctly represent the shared connections. There is also a PCM
> > connection for Bluetooth, but this is not covered in this patch.
> >
> > These boards all have a WiFi+BT module from AMPAK, which contains one or
> > two Broadcom chips, depending on the model. The older AP6210 contains
> > two, while the newer AP6212 and AP6330 contain just one, as they use
> > two-in-one combo chips.
> >
> > The Bluetooth side of the module is always connected to a UART on the
> > same pingroup as the SDIO pins for the WiFi side, in a 4 wire
> > configuration. Power to the VBAT and VDDIO pins are provided either by
> > the PMIC, using one or several of its regulator outputs, or other fixed
> > regulators on the board. The VBAT and VDDIO pins are shared with the
> > WiFi side, which would correspond to vmmc-supply and vqmmc-supply in the
> > mmc host node. A clock output from the SoC or the external X-Powers RTC
> > provides the LPO low power clock at 32.768 kHz.
> >
> > All the boards covered in this patch are ones that do not require extra
> > changes to the SoC's dtsi file. For the remaining boards that I have
> > worked on, properties or device nodes for the LPO clock's source are
> > missing.
> >
> > Signed-off-by: Chen-Yu Tsai
> > ---
> > arch/arm/boot/dts/sun7i-a20-cubietruck.dts| 22 +++
> > arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 18 +++
> > .../boot/dts/sun8i-a83t-cubietruck-plus.dts | 18 +++
> > arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 14
> > 4 files changed, 72 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> > b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> > index 5649161de1d7..ccbf3b7a062b 100644
> > --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> > +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> > @@ -103,6 +103,8 @@
> > pinctrl-names = "default";
> > pinctrl-0 = <_pwrseq_pin_cubietruck>;
> > reset-gpios = < 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
> > + clocks = < CLK_OUT_A>;
> > + clock-names = "ext_clock";
> > };
> >
> > sound {
> > @@ -246,6 +248,10 @@
> > };
> >
> > {
> > + /* Pin outputs low power clock for WiFi and BT */
> > + pinctrl-0 = <_out_a_pins_a>;
> > + pinctrl-names = "default";
> > +
>
> I guess we should make it clear in the comment why it cannot be tied
> to both devices.
I think it's a limitation of the implementation. But it's also a shared output,
so putting it at the source probably makes more sense. So I think it's more like
a preference rather than a hard limitation.
> > ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
> > pins = "PH12";
> > function = "gpio_out";
> > @@ -350,6 +356,22 @@
> > status = "okay";
> > };
> >
> > + {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_pins_a>;
> > + status = "okay";
>
> No RTS/CTS?
Missed this one. This was your Cubietruck patch squashed in with the rest.
ChenYu
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