On Thu, Jan 2, 2020 at 9:17 PM Maxime Ripard wrote:
>
> On Thu, Jan 02, 2020 at 09:10:31PM +0530, Jagan Teki wrote:
> > On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote:
> > >
> > > On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> > > > TCON LCD0, LCD1 in allwinner R40, are used
On Thu, Jan 2, 2020 at 4:33 PM Maxime Ripard wrote:
>
> On Tue, Dec 31, 2019 at 06:35:25PM +0530, Jagan Teki wrote:
> > The MIPI DSI PHY controller on Allwinner R40 is similar
> > on the one on A31.
> >
> > Add R40 compatible and append A31 compatible as fallback.
> >
> > Signed-off-by: Jagan
On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote:
>
> On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> > TCON LCD0, LCD1 in allwinner R40, are used for managing
> > LCD interfaces like RGB, LVDS and DSI.
> >
> > Like TCON TV0, TV1 these LCD0, LCD1 are also managed via
> > tcon top.
On Sat, 2019-12-14 at 22:24 -0600, Samuel Holland wrote:
> Allwinner sun6i, sun8i, sun9i, and sun50i SoCs contain a hardware
> message box used for communication between the ARM CPUs and the ARISC
> management coprocessor. This mailbox contains 8 unidirectional
> 4-message FIFOs.
>
> Add a driver
On Thu, Jan 2, 2020 at 6:42 PM Andre Przywara wrote:
>
> On Thu, 2 Jan 2020 10:57:11 +0100
> Maxime Ripard wrote:
>
> Hi Maxime,
>
> thanks for having a look!
>
> > On Thu, Jan 02, 2020 at 01:26:57AM +, Andre Przywara wrote:
> > > The Allwinner R40 SoC contains four SPI controllers, using
On Thu, 2 Jan 2020 10:57:11 +0100
Maxime Ripard wrote:
Hi Maxime,
thanks for having a look!
> On Thu, Jan 02, 2020 at 01:26:57AM +, Andre Przywara wrote:
> > The Allwinner R40 SoC contains four SPI controllers, using the newer
> > sun6i design (but at the legacy addresses).
> > The
