[linux-sunxi] Re: [PATCH 3/3] dt-bindings: arm: sunxi: note that old PineTab compatible has old panel
On Thu, 10 Dec 2020 16:45:58 +0800, Icenowy Zheng wrote: > As the old LCD panel used by PineTab developer samples are discontinued, > there won't be furtherly any more units of the sample, and this should > be noted in the document. > > Signed-off-by: Icenowy Zheng > --- > Documentation/devicetree/bindings/arm/sunxi.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Rob Herring -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211033953.GA3593536%40robh.at.kernel.org.
[linux-sunxi] Re: [PATCH 1/3] dt-bindings: arm: sunxi: add PineTab new panel DT binding
On Thu, 10 Dec 2020 16:42:32 +0800, Icenowy Zheng wrote: > Early adopters' PineTabs (and all further releases) will have a new LCD > panel different with the one that is used when in development (because > the old panel's supply discontinued). > > Add a new DT compatible for it. > > Signed-off-by: Icenowy Zheng > --- > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + > 1 file changed, 5 insertions(+) > Reviewed-by: Rob Herring -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211033937.GA3593126%40robh.at.kernel.org.
[linux-sunxi] Re: [PATCH v2 16/19] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation
On Sat, 28 Nov 2020 15:28:36 +0100, Paul Kocialkowski wrote: > This introduces YAML bindings documentation for the A83T MIPI CSI-2 > controller. > > Signed-off-by: Paul Kocialkowski > --- > .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++ > 1 file changed, 147 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml > Reviewed-by: Rob Herring -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211031207.GA3555125%40robh.at.kernel.org.
[linux-sunxi] [PATCH v2 21/21] arm64: dts: allwinner: Add OrangePi Zero 2 .dts
The OrangePi Zero 2 is a development board with the new H616 SoC.
It features the usual connectors used on those small boards, and comes
with the AXP305, which seems to be compatible with the AXP805.
For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 240 ++
2 files changed, 241 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index 211d1e9d4701..0cf8299b1ce7 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -35,3 +35,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
new file mode 100644
index ..2afc036059b4
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2020 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include
+#include
+#include
+
+/ {
+ model = "OrangePi Zero2";
+ compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ function = LED_FUNCTION_POWER;
+ color = ;
+ gpios = < 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ default-state = "on";
+ };
+
+ status {
+ function = LED_FUNCTION_STATUS;
+ color = ;
+ gpios = < 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_vcc5v>;
+ enable-active-high;
+ gpio = < 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ status = "okay";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <_rgmii_phy>;
+ phy-supply = <_dcdce>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+ {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+ {
+ vmmc-supply = <_dcdce>;
+ cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_i2c {
+ status = "okay";
+
+ axp305: pmic@36 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+"x-powers,axp806";
+ reg = <0x36>;
+
+ x-powers,self-working-mode;
+ vina-supply = <_vcc5v>;
+ vinb-supply = <_vcc5v>;
+ vinc-supply = <_vcc5v>;
+ vind-supply = <_vcc5v>;
+ vine-supply = <_vcc5v>;
+ aldoin-supply = <_vcc5v>;
+ bldoin-supply = <_vcc5v>;
+ cldoin-supply = <_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-sys";
+ };
+
+ reg_aldo2: aldo2 { /* 3.3V on headers */
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+
[linux-sunxi] [PATCH v2 20/21] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding
Signed-off-by: Andre Przywara --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index cab8e1b6417b..5f8b5c896e66 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -894,4 +894,9 @@ properties: - const: xunlong,orangepi-zero-plus2-h3 - const: allwinner,sun8i-h3 + - description: Xunlong OrangePi Zero 2 +items: + - const: xunlong,orangepi-zero2 + - const: allwinner,sun50i-h616 + additionalProperties: true -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211011934.6171-21-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v2 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
This (relatively) new SoC is similar to the H6, but drops the (broken)
PCIe support and the USB 3.0 controller. It also gets the management
controller removed, which in turn removes *some*, but not all of the
devices formerly dedicated to the ARISC (CPUS).
There does not seem to be an extra interrupt controller anymore, also
it lacks the corresponding NMI pin, so no interrupts for the PMIC.
Signed-off-by: Andre Przywara
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 715 ++
1 file changed, 715 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
new file mode 100644
index ..7202632b061b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -0,0 +1,715 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Arm Ltd.
+// based on the H6 dtsi, which is:
+// Copyright (C) 2017 Icenowy Zheng
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 512KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@4000 {
+ reg = <0x0 0x4000 0x0 0x8>;
+ no-map;
+ };
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ,
+,
+,
+;
+ interrupt-affinity = <>, <>, <>, <>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ arm,no-tick-in-suspend;
+ interrupts = ,
+,
+,
+;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x4000>;
+
+ syscon: syscon@300 {
+ compatible = "allwinner,sun50i-h616-system-control";
+ reg = <0x0300 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@28000 {
+ compatible = "mmio-sram";
+ reg = <0x00028000 0x3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00028000 0x3>;
+ };
+ };
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h616-ccu";
+ reg = <0x03001000 0x1000>;
+ clocks = <>, < 0>, < 2>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ watchdog: watchdog@30090a0 {
+ compatible = "allwinner,sun50i-h616-wdt",
+"allwinner,sun6i-a31-wdt";
+
[linux-sunxi] [PATCH v2 18/21] dt-bindings: allwinner: Add H616 compatible strings
Add simple "allwinner,sun50i-h616-xxx" compatible names to existing bindings, and pair them with an existing fallback compatible string, as the devices are compatible. This covers I2C, infrared, RTC and SPI. Use enums to group all compatible devices together. Signed-off-by: Andre Przywara --- .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 21 +++ .../media/allwinner,sun4i-a10-ir.yaml | 16 ++ .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 3 +++ .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 + 4 files changed, 17 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index 5b5ae402f97a..eb72dd571def 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -18,21 +18,14 @@ properties: - const: allwinner,sun4i-a10-i2c - const: allwinner,sun6i-a31-i2c - items: - - const: allwinner,sun8i-a23-i2c + - enum: + - allwinner,sun8i-a23-i2c + - allwinner,sun8i-a83t-i2c + - allwinner,sun50i-a64-i2c + - allwinner,sun50i-a100-i2c + - allwinner,sun50i-h6-i2c + - allwinner,sun50i-h616-i2c - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun8i-a83t-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-a64-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-a100-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-h6-i2c - - const: allwinner,sun6i-a31-i2c - - const: marvell,mv64xxx-i2c - const: marvell,mv78230-i2c - const: marvell,mv78230-a0-i2c diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml index 5fa19d4aeaf3..6d8395d6bca0 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml @@ -20,16 +20,12 @@ properties: - const: allwinner,sun5i-a13-ir - const: allwinner,sun6i-a31-ir - items: - - const: allwinner,sun8i-a83t-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun8i-r40-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun50i-a64-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun50i-h6-ir + - enum: + - allwinner,sun8i-a83t-ir + - allwinner,sun8i-r40-ir + - allwinner,sun50i-a64-ir + - allwinner,sun50i-h6-ir + - allwinner,sun50i-h616-ir - const: allwinner,sun6i-a31-ir reg: diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index 37c2a601c3fa..97928efd2bc9 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -26,6 +26,9 @@ properties: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc - const: allwinner,sun50i-h6-rtc + - items: + - const: allwinner,sun50i-h616-rtc + - const: allwinner,sun50i-h6-rtc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 7866a655d81c..908248260afa 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -25,6 +25,7 @@ properties: - enum: - allwinner,sun8i-r40-spi - allwinner,sun50i-h6-spi + - allwinner,sun50i-h616-spi - const: allwinner,sun8i-h3-spi reg: -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211011934.6171-19-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v2 17/21] dt-bindings: watchdog: sun4i: Add H616 compatible string
Use enums to group all compatible devices together on the way. Signed-off-by: Andre Przywara --- .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 5ac607de8be4..9aa3c313c49f 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -19,13 +19,11 @@ properties: - const: allwinner,sun4i-a10-wdt - const: allwinner,sun6i-a31-wdt - items: - - const: allwinner,sun50i-a64-wdt - - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,sun50i-a100-wdt - - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,sun50i-h6-wdt + - enum: + - allwinner,sun50i-a64-wdt + - allwinner,sun50i-a100-wdt + - allwinner,sun50i-h6-wdt + - allwinner,sun50i-h616-wdt - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,suniv-f1c100s-wdt -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211011934.6171-18-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v2 16/21] dt-bindings: watchdog: sun4i: Add A100 compatible
From: Yangtao Li Add a binding for A100's watchdog controller. Signed-off-by: Yangtao Li Acked-by: Rob Herring Signed-off-by: Andre Przywara --- .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index e8f226376108..5ac607de8be4 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -21,6 +21,9 @@ properties: - items: - const: allwinner,sun50i-a64-wdt - const: allwinner,sun6i-a31-wdt + - items: + - const: allwinner,sun50i-a100-wdt + - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,sun50i-h6-wdt - const: allwinner,sun6i-a31-wdt -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211011934.6171-17-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v2 15/21] phy: sun4i-usb: Add support for the H616 USB PHY
The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and clears a different bit in the
PMU_UNK1 register like the A100.
Name all those properties in a new config struct and assign a new
compatible name to it.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 4ba0699e0bb4..671c5cc59433 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -968,6 +968,16 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.missing_phys = BIT(1) | BIT(2),
};
+static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
+ .num_phys = 4,
+ .type = sun50i_h6_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .phy0_dual_route = true,
+ .pmu_unk1_clrbits = BIT(3),
+};
+
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = _a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = _a13_cfg },
@@ -982,6 +992,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] =
{
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = _a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = _h6_cfg },
+ { .compatible = "allwinner,sun50i-h616-usb-phy", .data =
_h616_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.17.5
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[linux-sunxi] [PATCH v2 14/21] phy: sun4i-usb: Rework "pmu_unk1" handling
Newer SoCs (A100, H616) need to clear a different bit in our "unknown"
PMU PHY register.
Generalise the existing code by allowing configs to specify a bitmask
of bits to clear.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 28 +++
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 651d5e2a25ce..4ba0699e0bb4 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -115,9 +115,9 @@ struct sun4i_usb_phy_cfg {
int hsic_index;
enum sun4i_usb_phy_type type;
u32 disc_thresh;
+ u32 pmu_unk1_clrbits;
u8 phyctl_offset;
bool dedicated_clocks;
- bool enable_pmu_unk1;
bool phy0_dual_route;
int missing_phys;
};
@@ -288,6 +288,12 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ if (phy->pmu && data->cfg->pmu_unk1_clrbits) {
+ val = readl(phy->pmu + REG_PMU_UNK1);
+ val &= ~data->cfg->pmu_unk1_clrbits;
+ writel(val, phy->pmu + REG_PMU_UNK1);
+ }
+
if (data->cfg->type == sun8i_a83t_phy ||
data->cfg->type == sun50i_h6_phy) {
if (phy->index == 0) {
@@ -297,11 +303,6 @@ static int sun4i_usb_phy_init(struct phy *_phy)
writel(val, data->base + data->cfg->phyctl_offset);
}
} else {
- if (phy->pmu && data->cfg->enable_pmu_unk1) {
- val = readl(phy->pmu + REG_PMU_UNK1);
- writel(val & ~2, phy->pmu + REG_PMU_UNK1);
- }
-
/* Enable USB 45 Ohm resistor calibration */
if (phy->index == 0)
sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
@@ -867,7 +868,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
@@ -876,7 +876,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
@@ -885,7 +884,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
@@ -894,7 +892,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
@@ -903,7 +900,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
@@ -912,7 +908,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
@@ -929,7 +924,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .pmu_unk1_clrbits = BIT(1),
.phy0_dual_route = true,
};
@@ -939,7 +934,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .pmu_unk1_clrbits = BIT(1),
.phy0_dual_route = true,
};
@@ -949,7 +944,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .pmu_unk1_clrbits = BIT(1),
.phy0_dual_route = true,
};
@@ -959,7 +954,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .pmu_unk1_clrbits = BIT(1),
.phy0_dual_route = true,
};
@@ -969,7 +964,6 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
.phy0_dual_route = true,
.missing_phys = BIT(1) | BIT(2),
};
--
2.17.5
--
[linux-sunxi] [PATCH v2 13/21] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register
The Allwinner H616 SoC has two EMAC controllers, with the second one
being tied to the internal PHY, but also using a separate EMAC clock
register.
To tell the driver about which clock register to use, we add a parameter
to our syscon phandle. The driver will use this value as an index into
the regmap, so that we can address more than the first register, if
needed.
Signed-off-by: Andre Przywara
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 58e0511badba..00c10ec7b693 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -1129,6 +1129,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
struct stmmac_priv *priv;
struct net_device *ndev;
struct regmap *regmap;
+ struct reg_field syscon_field;
+ u32 syscon_idx = 0;
ret = stmmac_get_platform_resources(pdev, _res);
if (ret)
@@ -1190,8 +1192,12 @@ static int sun8i_dwmac_probe(struct platform_device
*pdev)
return ret;
}
- gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
-
*gmac->variant->syscon_field);
+ syscon_field = *gmac->variant->syscon_field;
+ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1,
+_idx);
+ if (!ret)
+ syscon_field.reg += syscon_idx * sizeof(u32);
+ gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, syscon_field);
if (IS_ERR(gmac->regmap_field)) {
ret = PTR_ERR(gmac->regmap_field);
dev_err(dev, "Unable to map syscon register: %d\n", ret);
@@ -1263,6 +1269,8 @@ static const struct of_device_id sun8i_dwmac_match[] = {
.data = _variant_a64 },
{ .compatible = "allwinner,sun50i-h6-emac",
.data = _variant_h6 },
+ { .compatible = "allwinner,sun50i-h616-emac",
+ .data = _variant_h6 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.17.5
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[linux-sunxi] [PATCH v2 12/21] soc: sunxi: sram: Add support for more than one EMAC clock
The Allwinner H616 adds a second EMAC clock register at offset 0x34, for
controlling the second EMAC in this chip.
Allow to extend the regmap in this case, to cover more than the current
4 bytes exported.
Signed-off-by: Andre Przywara
---
drivers/soc/sunxi/sunxi_sram.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index d4c7bd59429e..42833e33a96c 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -283,7 +283,7 @@ int sunxi_sram_release(struct device *dev)
EXPORT_SYMBOL(sunxi_sram_release);
struct sunxi_sramc_variant {
- bool has_emac_clock;
+ int num_emac_clocks;
};
static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
@@ -291,20 +291,31 @@ static const struct sunxi_sramc_variant
sun4i_a10_sramc_variant = {
};
static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
- .has_emac_clock = true,
+ .num_emac_clocks = 1,
};
static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
- .has_emac_clock = true,
+ .num_emac_clocks = 1,
+};
+
+static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
+ .num_emac_clocks = 2,
};
#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
unsigned int reg)
{
- if (reg == SUNXI_SRAM_EMAC_CLOCK_REG)
- return true;
- return false;
+ const struct sunxi_sramc_variant *variant;
+
+ variant = of_device_get_match_data(dev);
+
+ if (reg < SUNXI_SRAM_EMAC_CLOCK_REG)
+ return false;
+ if (reg > SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
+ return false;
+
+ return true;
}
static struct regmap_config sunxi_sram_emac_clock_regmap = {
@@ -312,7 +323,7 @@ static struct regmap_config sunxi_sram_emac_clock_regmap = {
.val_bits = 32,
.reg_stride = 4,
/* last defined register */
- .max_register = SUNXI_SRAM_EMAC_CLOCK_REG,
+ .max_register = SUNXI_SRAM_EMAC_CLOCK_REG + 4,
/* other devices have no business accessing other registers */
.readable_reg = sunxi_sram_regmap_accessible_reg,
.writeable_reg = sunxi_sram_regmap_accessible_reg,
@@ -343,7 +354,7 @@ static int sunxi_sram_probe(struct platform_device *pdev)
if (!d)
return -ENOMEM;
- if (variant->has_emac_clock) {
+ if (variant->num_emac_clocks > 0) {
emac_clock = devm_regmap_init_mmio(>dev, base,
_sram_emac_clock_regmap);
@@ -387,6 +398,10 @@ static const struct of_device_id sunxi_sram_dt_match[] = {
.compatible = "allwinner,sun50i-h5-system-control",
.data = _a64_sramc_variant,
},
+ {
+ .compatible = "allwinner,sun50i-h616-system-control",
+ .data = _h616_sramc_variant,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
--
2.17.5
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[linux-sunxi] [PATCH v2 11/21] dt-bindings: sram: sunxi-sram: Add H616 compatible string
The H616 adds a second EMAC clock register. We don't know about the exact SRAM properties yet, so this gets omitted for now. Signed-off-by: Andre Przywara --- .../bindings/sram/allwinner,sun4i-a10-system-control.yaml| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index b66a07e21d1e..1c426c211e36 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -49,6 +49,7 @@ properties: - items: - const: allwinner,suniv-f1c100s-system-control - const: allwinner,sun4i-a10-system-control + - const: allwinner,sun50i-h616-system-control reg: maxItems: 1 -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211011934.6171-12-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v2 10/21] mfd: axp20x: Allow AXP chips without interrupt lines
Currently the AXP chip requires to have its IRQ line connected to some
interrupt controller, and will fail probing when this is not the case.
On a new Allwinner SoC (H616) there is no NMI pin anymore, so the
interrupt functionality of the AXP chip is simply not available.
Check whether the DT describes the AXP chip as an interrupt controller
before trying to register the irqchip, to avoid probe failures on
setups without an interrupt.
Signed-off-by: Andre Przywara
---
drivers/mfd/axp20x.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index aa59496e4376..a52595c49d40 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -959,12 +959,17 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
}
- ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
- IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
- -1, axp20x->regmap_irq_chip, >regmap_irqc);
- if (ret) {
- dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
- return ret;
+ if (!axp20x->dev->of_node ||
+ of_property_read_bool(axp20x->dev->of_node,
"interrupt-controller")) {
+ ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
+ IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
+ -1, axp20x->regmap_irq_chip,
+ >regmap_irqc);
+ if (ret) {
+ dev_err(axp20x->dev, "failed to add irq chip: %d\n",
+ ret);
+ return ret;
+ }
}
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
--
2.17.5
--
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[linux-sunxi] [PATCH v2 09/21] mmc: sunxi: add support for A100 mmc controller
From: Yangtao Li
This patch adds support for A100 MMC controller, which use word address
for internal dma.
Signed-off-by: Yangtao Li
Signed-off-by: Andre Przywara
---
drivers/mmc/host/sunxi-mmc.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index fc62773602ec..1518b64112b7 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -244,6 +244,7 @@ struct sunxi_idma_des {
struct sunxi_mmc_cfg {
u32 idma_des_size_bits;
+ u32 idma_des_shift;
const struct sunxi_mmc_clk_delay *clk_delays;
/* does the IP block support autocalibration? */
@@ -343,7 +344,7 @@ static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
/* Enable CEATA support */
mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
/* Set DMA descriptor list base address */
- mmc_writel(host, REG_DLBA, host->sg_dma);
+ mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift);
rval = mmc_readl(host, REG_GCTRL);
rval |= SDXC_INTERRUPT_ENABLE_BIT;
@@ -373,8 +374,10 @@ static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host
*host,
next_desc += sizeof(struct sunxi_idma_des);
pdes[i].buf_addr_ptr1 =
- cpu_to_le32(sg_dma_address(>sg[i]));
- pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
+ cpu_to_le32(sg_dma_address(>sg[i]) >>
+ host->cfg->idma_des_shift);
+ pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >>
+ host->cfg->idma_des_shift);
}
pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
@@ -1178,6 +1181,23 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
.needs_new_timings = true,
};
+static const struct sunxi_mmc_cfg sun50i_a100_cfg = {
+ .idma_des_size_bits = 16,
+ .idma_des_shift = 2,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+ .mask_data0 = true,
+ .needs_new_timings = true,
+};
+
+static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {
+ .idma_des_size_bits = 13,
+ .idma_des_shift = 2,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+ .needs_new_timings = true,
+};
+
static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-mmc", .data = _a10_cfg },
{ .compatible = "allwinner,sun5i-a13-mmc", .data = _a13_cfg },
@@ -1186,6 +1206,8 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun9i-a80-mmc", .data = _a80_cfg },
{ .compatible = "allwinner,sun50i-a64-mmc", .data = _a64_cfg },
{ .compatible = "allwinner,sun50i-a64-emmc", .data =
_a64_emmc_cfg },
+ { .compatible = "allwinner,sun50i-a100-mmc", .data = _a100_cfg },
+ { .compatible = "allwinner,sun50i-a100-emmc", .data =
_a100_emmc_cfg },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
--
2.17.5
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[linux-sunxi] [PATCH v2 08/21] dt-bindings: mmc: sunxi: Add Allwinner A100 and H616 compatibles
From: Yangtao Li Add binding for A100's and H616's mmc and emmc controller. Signed-off-by: Yangtao Li Signed-off-by: Andre Przywara --- .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index e82c9a07b6fb..e75b3a8ba816 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -26,6 +26,8 @@ properties: - const: allwinner,sun9i-a80-mmc - const: allwinner,sun50i-a64-emmc - const: allwinner,sun50i-a64-mmc + - const: allwinner,sun50i-a100-emmc + - const: allwinner,sun50i-a100-mmc - items: - const: allwinner,sun8i-a83t-mmc - const: allwinner,sun7i-a20-mmc @@ -47,6 +49,12 @@ properties: - items: - const: allwinner,sun50i-h6-mmc - const: allwinner,sun50i-a64-mmc + - items: + - const: allwinner,sun50i-h616-emmc + - const: allwinner,sun50i-a100-emmc + - items: + - const: allwinner,sun50i-h616-mmc + - const: allwinner,sun50i-a100-mmc reg: maxItems: 1 -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211011934.6171-9-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v2 07/21] clk: sunxi-ng: Add support for the Allwinner H616 CCU
While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.
Derived from the H6 clock driver, and adjusted according to the manual.
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi-ng/Kconfig|5 +
drivers/clk/sunxi-ng/Makefile |1 +
drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1150 +++
drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 56 +
include/dt-bindings/clock/sun50i-h616-ccu.h | 115 ++
include/dt-bindings/reset/sun50i-h616-ccu.h | 70 ++
6 files changed, 1397 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index feeb8d2074ee..cd46d8853876 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -32,6 +32,11 @@ config SUN50I_H6_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+config SUN50I_H616_CCU
+ bool "Support for the Allwinner H616 CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
config SUN50I_H6_R_CCU
bool "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 3eb5cff40eac..96c324306d97 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
+obj-$(CONFIG_SUN50I_H616_CCU) += ccu-sun50i-h616.o
obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
new file mode 100644
index ..19db5636a80d
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
@@ -0,0 +1,1150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Arm Ltd.
+ * Based on the H6 CCU driver, which is:
+ * Copyright (c) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-h616.h"
+
+/*
+ * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
+ * P should only be used for output frequencies lower than 288 MHz.
+ *
+ * For now we can just model it as a multiplier clock, and force P to /1.
+ *
+ * The M factor is present in the register's description, but not in the
+ * frequency formula, and it's documented as "M is only used for backdoor
+ * testing", so it's not modelled and then force to 0.
+ */
+#define SUN50I_H616_PLL_CPUX_REG 0x000
+static struct ccu_mult pll_cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .common = {
+ .reg= 0x000,
+ .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
+ _mult_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
+#define SUN50I_H616_PLL_DDR0_REG 0x010
+static struct ccu_nkmp pll_ddr0_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
+ .common = {
+ .reg= 0x010,
+ .hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
+ _nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+#define SUN50I_H616_PLL_DDR1_REG 0x018
+static struct ccu_nkmp pll_ddr1_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
+ .common = {
+ .reg= 0x018,
+ .hw.init= CLK_HW_INIT("pll-ddr1", "osc24M",
+ _nkmp_ops,
+
[linux-sunxi] [PATCH v2 06/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi-ng/Kconfig | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +-
3 files changed, 49 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index ce5f5847d5d3..feeb8d2074ee 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -33,7 +33,7 @@ config SUN50I_H6_CCU
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_H6_R_CCU
- bool "Support for the Allwinner H6 PRCM CCU"
+ bool "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 50f8d1bc7046..0ca35f383975 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -136,6 +136,15 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
_clk.common,
};
+static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
+ _apb1_clk.common,
+ _apb2_clk.common,
+ _apb1_twd_clk.common,
+ _apb2_i2c_clk.common,
+ _apb1_ir_clk.common,
+ _clk.common,
+};
+
static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
.hws= {
[CLK_AR100] = _clk.common.hw,
@@ -152,7 +161,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
[CLK_IR]= _clk.common.hw,
[CLK_W1]= _clk.common.hw,
},
- .num= CLK_NUMBER,
+ .num= CLK_NUMBER_H6,
+};
+
+static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
+ .hws= {
+ [CLK_R_AHB] = _ahb_clk.hw,
+ [CLK_R_APB1]= _apb1_clk.common.hw,
+ [CLK_R_APB2]= _apb2_clk.common.hw,
+ [CLK_R_APB1_TWD]= _apb1_twd_clk.common.hw,
+ [CLK_R_APB2_I2C]= _apb2_i2c_clk.common.hw,
+ [CLK_R_APB1_IR] = _apb1_ir_clk.common.hw,
+ [CLK_IR]= _clk.common.hw,
+ },
+ .num= CLK_NUMBER_H616,
};
static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
@@ -165,6 +187,12 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_W1] = { 0x1ec, BIT(16) },
};
+static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
+ [RST_R_APB1_TWD]= { 0x12c, BIT(16) },
+ [RST_R_APB2_I2C]= { 0x19c, BIT(16) },
+ [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
+};
+
static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
.ccu_clks = sun50i_h6_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
@@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
.num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
};
+static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
+ .ccu_clks = sun50i_h616_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks),
+
+ .hw_clks= _h616_r_hw_clks,
+
+ .resets = sun50i_h616_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
+};
+
static void __init sunxi_r_ccu_init(struct device_node *node,
const struct sunxi_ccu_desc *desc)
{
@@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct
device_node *node)
}
CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
sun50i_h6_r_ccu_setup);
+
+static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
+{
+ sunxi_r_ccu_init(node, _h616_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
+ sun50i_h616_r_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
index 782117dc0b28..128302696ca1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
@@ -14,6 +14,7 @@
#define CLK_R_APB2 3
-#define CLK_NUMBER (CLK_W1 + 1)
+#define CLK_NUMBER_H6 (CLK_W1 + 1)
+#define CLK_NUMBER_H616(CLK_IR + 1)
#endif /* _CCU_SUN50I_H6_R_H */
--
2.17.5
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[linux-sunxi] [PATCH v2 05/21] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616
Signed-off-by: Andre Przywara --- .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml index 3b45344ed758..b7e891803bb4 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -41,6 +41,8 @@ properties: - allwinner,sun50i-h5-ccu - allwinner,sun50i-h6-ccu - allwinner,sun50i-h6-r-ccu + - allwinner,sun50i-h616-ccu + - allwinner,sun50i-h616-r-ccu - allwinner,suniv-f1c100s-ccu - nextthing,gr8-ccu -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211011934.6171-6-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v2 04/21] pinctrl: sunxi: Add support for the Allwinner H616-R pin controller
There are only two pins left now, used to connect to the PMIC via I2C.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Reviewed-by: Jernej Skrabec
---
drivers/pinctrl/sunxi/Kconfig | 5 ++
drivers/pinctrl/sunxi/Makefile| 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c | 54 +++
3 files changed, 60 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 73e88ce71a48..33751a6a0757 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -124,4 +124,9 @@ config PINCTRL_SUN50I_H616
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H616_R
+ bool "Support for the Allwinner H616 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 5359327a3c8f..d3440c42b9d6 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -24,5 +24,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H5) +=
pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6)+= pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o
+obj-$(CONFIG_PINCTRL_SUN50I_H616_R)+= pinctrl-sun50i-h616-r.o
obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
new file mode 100644
index ..52783dd98b18
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H616 R_PIO pin controller driver
+ *
+ * Copyright (C) 2020 Arm Ltd.
+ * Based on former work, which is:
+ * Copyright (C) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_h616_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_i2c")),/* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_i2c")),/* SDA */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_h616_r_pinctrl_data = {
+ .pins = sun50i_h616_r_pins,
+ .npins = ARRAY_SIZE(sun50i_h616_r_pins),
+ .pin_base = PL_BASE,
+};
+
+static int sun50i_h616_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ _h616_r_pinctrl_data);
+}
+
+static const struct of_device_id sun50i_h616_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-h616-r-pinctrl", },
+ {}
+};
+
+static struct platform_driver sun50i_h616_r_pinctrl_driver = {
+ .probe = sun50i_h616_r_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-h616-r-pinctrl",
+ .of_match_table = sun50i_h616_r_pinctrl_match,
+ },
+};
+builtin_platform_driver(sun50i_h616_r_pinctrl_driver);
--
2.17.5
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[linux-sunxi] [PATCH v2 03/21] pinctrl: sunxi: Add support for the Allwinner H616 pin controller
Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not
mentioned in the manual.
Signed-off-by: Andre Przywara
---
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 548
3 files changed, 554 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 593293584ecc..73e88ce71a48 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -119,4 +119,9 @@ config PINCTRL_SUN50I_H6_R
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H616
+ bool "Support for the Allwinner H616 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 8b7ff0dc3bdf..5359327a3c8f 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -23,5 +23,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_V3S) +=
pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5)+= pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6)+= pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
+obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o
obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
new file mode 100644
index ..02ff80bf163a
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H616 SoC pinctrl driver.
+ *
+ * Copyright (C) 2020 Arm Ltd.
+ * based on the H6 pinctrl driver
+ * Copyright (C) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin h616_pins[] = {
+ /* Internal connection to the AC200 part */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ECRS_DV */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ERXERR */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ETXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ETXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ETXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ETXEN */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
+ SUNXI_FUNCTION(0x2, "emac1")),/* EMDC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
+ SUNXI_FUNCTION(0x2, "emac1")),/* EMDIO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
+ SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
+ SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
+ SUNXI_FUNCTION(0x2, "pwm5")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
+ SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PC_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PC_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PC_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CE1
[linux-sunxi] [PATCH v2 02/21] dt-bindings: pinctrl: Add Allwinner H616 compatible strings
A new SoC, a new compatible string. Also we were too miserly with just allowing seven interrupt banks. Signed-off-by: Andre Przywara --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 5240487dfe50..292b05d9ed08 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -53,6 +53,8 @@ properties: - allwinner,sun50i-h5-pinctrl - allwinner,sun50i-h6-pinctrl - allwinner,sun50i-h6-r-pinctrl + - allwinner,sun50i-h616-pinctrl + - allwinner,sun50i-h616-r-pinctrl - allwinner,suniv-f1c100s-pinctrl - nextthing,gr8-pinctrl @@ -61,7 +63,7 @@ properties: interrupts: minItems: 1 -maxItems: 7 +maxItems: 8 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. @@ -91,7 +93,7 @@ properties: bank found in the controller $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 -maxItems: 5 +maxItems: 8 patternProperties: # It's pretty scary, but the basic idea is that: @@ -145,6 +147,18 @@ allOf: # boards are defining it at the moment so it would generate a lot of # warnings. + - if: + properties: +compatible: + enum: +- allwinner,sun50i-h616-pinctrl + +then: + properties: +interrupts: + minItems: 8 + maxItems: 8 + - if: properties: compatible: -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211011934.6171-3-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v2 01/21] clk: sunxi-ng: h6: Fix clock divider range on some clocks
While comparing clocks between the H6 and H616, some of the M factor
ranges were found to be wrong: the manual says they are only covering
two bits [1:0], but our code had "5" in the number-of-bits field.
By writing 0xff into that register in U-Boot and via FEL, it could be
confirmed that bits [4:2] are indeed masked off, so the manual is right.
Change to number of bits in the affected clock's description.
Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Andre Przywara
Reviewed-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index f2497d0a4683..d0565d378ea2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -237,7 +237,7 @@ static const char * const psi_ahb1_ahb2_parents[] = {
"osc24M", "osc32k",
static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
psi_ahb1_ahb2_parents,
0x510,
-0, 5, /* M */
+0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
@@ -246,19 +246,19 @@ static const char * const ahb3_apb1_apb2_parents[] = {
"osc24M", "osc32k",
"psi-ahb1-ahb2",
"pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
-0, 5, /* M */
+0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
-0, 5, /* M */
+0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
-0, 5, /* M */
+0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
--
2.17.5
--
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[linux-sunxi] [PATCH v2 00/21] arm64: sunxi: Initial Allwinner H616 SoC support
Hi, this is the quite expanded second version of the support series for the Allwinner H616 SoC. Besides many fixes for the bugs discovered by the diligent reviewers (many thanks for that!) this version adds some patches to support some slightly changed devices, like the second EMAC and the AXP not having an interrupt. Also I added quite some DT binding doc patches. USB still does not work, but I include the patches anyway, hoping that someone can help spotting the issue. For a more detailed changelog see below. Thanks! Andre == This series gathers patches to support the Allwinner H616 SoC. This is a rather uninspired SoC (Quad-A53 with the usual peripherals), but allows for some cheap development boards and TV boxes, and supports up to 4GB of DRAM. Various DT binding patches are sprinkled throughout the series, to add the new compatible names right before they are used. Patch 1/21 is the usual drive-by fix, discovered while staring at the H6 clock code. Patch 3 and 4 add pinctrl support, with the "-R" controller now being crippled down to two I2C pins only. If we grow tired of repeating this exercise for every new SoC variant, I am happy to revive my more versatile sunxi pinctrl driver effort from a few years back [1]. Patch 6 and 7 add clock support. For the -R clock this is shared with the H6 code, as the clocks are identical, with the H616 just having fewer of them. The main clocks are different enough to warrant a separate file. Patch 08/21 is pulling a patch from Yangtao's A100 series, since we need the same fix for MMC support. This will probably be merged separately, I just include this here to provide a bootable solution. Patch 10 teaches the AXP MFD driver to get along without having an interrupt, as the H616 apparently does not have an NMI controller anymore. Patch 12 and 13 add some tweaks to the syscon and EMAC driver, to deal with the second EMAC clock used for the second Ethernet controller. Patches 14 and 15 *try* to add USB support. The same approach works with the very similar U-Boot PHY driver, but for some reason still fail in Linux. Maybe someone spots the issue and can help fixing it? The remaining patches add DT bindings, which just add the new compatible string along with an existing name as a fallback string. Eventually we get the .dtsi for the SoC in patch 19, and the .dts for the OrangePi Zero2 board[2] in the last patch. We have U-Boot and Trusted-Firmware support in a working state, booting via FEL and even TFTPing kernels work already [3][4]. Many thanks to Jernej for his tremendous help on this, also for the awesome input and help from the #linux-sunxi Freenode channel. The whole series can also be found here: https://github.com/apritzel/linux/commits/h616-v2 Happy reviewing! Cheers, Andre [1] https://patchwork.ozlabs.org/project/linux-gpio/cover/20171113012523.2328-1-andre.przyw...@arm.com/ [2] https://linux-sunxi.org/Xunlong_Orange_Pi_Zero2 [3] https://github.com/jernejsk/u-boot/commits/h616-v1 [4] https://github.com/apritzel/arm-trusted-firmware/commits/h616-WIP Changelog v1 .. v2: - pinctrl: adjust irq bank map to cover undocumented GPIO bank IRQs - use differing h_i2s0 pin output names - r-ccu: fix number of used clocks - ccu: remove PLL-PERIPHy(4X) - ccu: fix gpu1 divider range - ccu: fix usb-phy3 parent - ccu: add missing TV clocks - ccu: rework to CLK_OF_DECLARE style - ccu: enable output bit for PLL clocks - ccu: renumber clocks - .dtsi: drop sun50i-a64-system-control fallback - .dtsi: drop unknown SRAM regions - .dtsi: add more (undocumented) GPIO interrupts - .dtsi: fix I2C3 pin names - .dtsi: use a100-emmc fallback for MMC2 - .dtsi: add second EMAC controller - .dtsi: use H3 MUSB controller fallback - .dtsi: fix frame size for USB PHY PMU registers - .dtsi: add USB0 PHY references - .dtsi: fix IR controller clock source - .dts: fix LED naming and swap pins - .dts: use 5V supply parent for USB supply - .dts: drop dummy IRQ for AXP - .dts: enable 3V3 header pin power rail - .dts: add SPI flash node - .dts: make USB-C port peripheral only - add IRQ-less AXP support - add two patches to support more than one EMAC clock - add patch to rework and extend USB PHY support - add DT binding documentation patches Andre Przywara (18): clk: sunxi-ng: h6: Fix clock divider range on some clocks dt-bindings: pinctrl: Add Allwinner H616 compatible strings pinctrl: sunxi: Add support for the Allwinner H616 pin controller pinctrl: sunxi: Add support for the Allwinner H616-R pin controller dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 clk: sunxi-ng: Add support for the Allwinner H616 R-CCU clk: sunxi-ng: Add support for the Allwinner H616 CCU mfd: axp20x: Allow AXP chips without interrupt lines dt-bindings: sram: sunxi-sram: Add H616 compatible string soc: sunxi: sram: Add support for more than one EMAC clock net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register phy: sun4i-usb: Rework "pmu_unk1"
Re: [linux-sunxi] [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU
On 10/12/2020 13:31, Icenowy Zheng wrote:
> 在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
>> While the clocks are fairly similar to the H6, many differ in tiny
>> details, so a separate clock driver seems indicated.
>>
>> Derived from the H6 clock driver, and adjusted according to the
>> manual.
>>
>> Signed-off-by: Andre Przywara
>> ---
>> drivers/clk/sunxi-ng/Kconfig|7 +-
>> drivers/clk/sunxi-ng/Makefile |1 +
>> drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1134
>> +++
>> drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 58 +
>> include/dt-bindings/clock/sun50i-h616-ccu.h | 110 ++
>> include/dt-bindings/reset/sun50i-h616-ccu.h | 67 ++
>> 6 files changed, 1376 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
>> create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
>> create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
>>
>> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-
>> ng/Kconfig
>> index ce5f5847d5d3..cd46d8853876 100644
>> --- a/drivers/clk/sunxi-ng/Kconfig
>> +++ b/drivers/clk/sunxi-ng/Kconfig
>> @@ -32,8 +32,13 @@ config SUN50I_H6_CCU
>> default ARM64 && ARCH_SUNXI
>> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>>
>> +config SUN50I_H616_CCU
>> +bool "Support for the Allwinner H616 CCU"
>> +default ARM64 && ARCH_SUNXI
>> +depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>> +
>> config SUN50I_H6_R_CCU
>> -bool "Support for the Allwinner H6 PRCM CCU"
>> +bool "Support for the Allwinner H6 and H616 PRCM CCU"
>> default ARM64 && ARCH_SUNXI
>> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>>
>> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-
>> ng/Makefile
>> index 3eb5cff40eac..96c324306d97 100644
>> --- a/drivers/clk/sunxi-ng/Makefile
>> +++ b/drivers/clk/sunxi-ng/Makefile
>> @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-
>> a64.o
>> obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
>> obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
>> obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
>> +obj-$(CONFIG_SUN50I_H616_CCU) += ccu-sun50i-h616.o
>> obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
>> obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
>> obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>> b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>> new file mode 100644
>> index ..3fbb258f0354
>> --- /dev/null
>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>> @@ -0,0 +1,1134 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2020 Arm Ltd.
>> + * Based on the H6 CCU driver, which is:
>> + * Copyright (c) 2017 Icenowy Zheng
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "ccu_common.h"
>> +#include "ccu_reset.h"
>> +
>> +#include "ccu_div.h"
>> +#include "ccu_gate.h"
>> +#include "ccu_mp.h"
>> +#include "ccu_mult.h"
>> +#include "ccu_nk.h"
>> +#include "ccu_nkm.h"
>> +#include "ccu_nkmp.h"
>> +#include "ccu_nm.h"
>> +
>> +#include "ccu-sun50i-h616.h"
>> +
>> +/*
>> + * The CPU PLL is actually NP clock, with P being /1, /2 or /4.
>> However
>> + * P should only be used for output frequencies lower than 288 MHz.
>> + *
>> + * For now we can just model it as a multiplier clock, and force P
>> to /1.
>> + *
>> + * The M factor is present in the register's description, but not in
>> the
>> + * frequency formula, and it's documented as "M is only used for
>> backdoor
>> + * testing", so it's not modelled and then force to 0.
>> + */
>> +#define SUN50I_H616_PLL_CPUX_REG0x000
>> +static struct ccu_mult pll_cpux_clk = {
>> +.enable = BIT(31),
>> +.lock = BIT(28),
>> +.mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
>> +.common = {
>> +.reg= 0x000,
>> +.hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
>> + _mult_ops,
>> + CLK_SET_RATE_UNGATE),
>> +},
>> +};
>> +
>> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K
>> */
>> +#define SUN50I_H616_PLL_DDR0_REG0x010
>> +static struct ccu_nkmp pll_ddr0_clk = {
>> +.enable = BIT(31),
>> +.lock = BIT(28),
>> +.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
>> +.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
>> +.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
>> +.common = {
>> +.reg= 0x010,
>> +.hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
>> + _nkmp_ops,
>> + CLK_SET_RATE_UNGATE),
>> +},
>> +};
>> +
>> +#define SUN50I_H616_PLL_DDR1_REG
Re: [linux-sunxi] [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU
在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
> While the clocks are fairly similar to the H6, many differ in tiny
> details, so a separate clock driver seems indicated.
>
> Derived from the H6 clock driver, and adjusted according to the
> manual.
>
> Signed-off-by: Andre Przywara
> ---
> drivers/clk/sunxi-ng/Kconfig|7 +-
> drivers/clk/sunxi-ng/Makefile |1 +
> drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1134
> +++
> drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 58 +
> include/dt-bindings/clock/sun50i-h616-ccu.h | 110 ++
> include/dt-bindings/reset/sun50i-h616-ccu.h | 67 ++
> 6 files changed, 1376 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
> create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
> create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-
> ng/Kconfig
> index ce5f5847d5d3..cd46d8853876 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -32,8 +32,13 @@ config SUN50I_H6_CCU
> default ARM64 && ARCH_SUNXI
> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>
> +config SUN50I_H616_CCU
> + bool "Support for the Allwinner H616 CCU"
> + default ARM64 && ARCH_SUNXI
> + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> +
> config SUN50I_H6_R_CCU
> - bool "Support for the Allwinner H6 PRCM CCU"
> + bool "Support for the Allwinner H6 and H616 PRCM CCU"
> default ARM64 && ARCH_SUNXI
> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-
> ng/Makefile
> index 3eb5cff40eac..96c324306d97 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU)+= ccu-sun50i-
> a64.o
> obj-$(CONFIG_SUN50I_A100_CCU)+= ccu-sun50i-a100.o
> obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
> obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
> +obj-$(CONFIG_SUN50I_H616_CCU)+= ccu-sun50i-h616.o
> obj-$(CONFIG_SUN50I_H6_R_CCU)+= ccu-sun50i-h6-r.o
> obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
> obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> new file mode 100644
> index ..3fbb258f0354
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2020 Arm Ltd.
> + * Based on the H6 CCU driver, which is:
> + * Copyright (c) 2017 Icenowy Zheng
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +
> +#include "ccu-sun50i-h616.h"
> +
> +/*
> + * The CPU PLL is actually NP clock, with P being /1, /2 or /4.
> However
> + * P should only be used for output frequencies lower than 288 MHz.
> + *
> + * For now we can just model it as a multiplier clock, and force P
> to /1.
> + *
> + * The M factor is present in the register's description, but not in
> the
> + * frequency formula, and it's documented as "M is only used for
> backdoor
> + * testing", so it's not modelled and then force to 0.
> + */
> +#define SUN50I_H616_PLL_CPUX_REG 0x000
> +static struct ccu_mult pll_cpux_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> + .common = {
> + .reg= 0x000,
> + .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
> + _mult_ops,
> + CLK_SET_RATE_UNGATE),
> + },
> +};
> +
> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K
> */
> +#define SUN50I_H616_PLL_DDR0_REG 0x010
> +static struct ccu_nkmp pll_ddr0_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
> + .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
> + .common = {
> + .reg= 0x010,
> + .hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
> + _nkmp_ops,
> + CLK_SET_RATE_UNGATE),
> + },
> +};
> +
> +#define SUN50I_H616_PLL_DDR1_REG 0x018
> +static struct ccu_nkmp pll_ddr1_clk = {
> + .enable = BIT(31),
> + .lock = BIT(28),
> + .n
[linux-sunxi] [PATCH 3/3] dt-bindings: arm: sunxi: note that old PineTab compatible has old panel
As the old LCD panel used by PineTab developer samples are discontinued, there won't be furtherly any more units of the sample, and this should be noted in the document. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/arm/sunxi.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 73a6c8421172..9f29b5811aa1 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -695,7 +695,7 @@ properties: - const: pine64,pinephone-1.2 - const: allwinner,sun50i-a64 - - description: Pine64 PineTab + - description: Pine64 PineTab (developers' sample with old discontinued LCD panel, discontinued) items: - const: pine64,pinetab - const: allwinner,sun50i-a64 -- 2.28.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201210084558.1917246-1-icenowy%40aosc.io.
[linux-sunxi] [PATCH 2/3] arm64: allwinner: dts: a64: add DT for PineTab with new LCD panel
Further released PineTabs will have a new LCD panel that is different
with the one used in developers' samples.
Add device tree for PineTab with the new panel.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../sun50i-a64-pinetab-new-panel.dts | 26 +++
2 files changed, 27 insertions(+)
create mode 100644
arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-new-panel.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index 211d1e9d4701..83c6d1ea197f 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-new-panel.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-new-panel.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-new-panel.dts
new file mode 100644
index ..f3da9653be3e
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-new-panel.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Icenowy Zheng
+ *
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64-pinetab.dts"
+
+/ {
+ model = "PineTab with new LCD panel";
+ compatible = "pine64,pinetab-new-panel", "allwinner,sun50i-a64";
+};
+
+ {
+ /delete-node/ panel@0;
+
+ panel@0 {
+ compatible = "feixin,k101-im2byl02";
+ reg = <0>;
+ power-supply = <_dc1sw>;
+ reset-gpios = < 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+ backlight = <>;
+ };
+};
--
2.28.0
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[linux-sunxi] [PATCH 1/3] dt-bindings: arm: sunxi: add PineTab new panel DT binding
Early adopters' PineTabs (and all further releases) will have a new LCD panel different with the one that is used when in development (because the old panel's supply discontinued). Add a new DT compatible for it. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 6db32fbf813f..73a6c8421172 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -700,6 +700,11 @@ properties: - const: pine64,pinetab - const: allwinner,sun50i-a64 + - description: Pine64 PineTab with new LCD panel +items: + - const: pine64,pinetab-new-panel + - const: allwinner,sun50i-a64 + - description: Pine64 SoPine Baseboard items: - const: pine64,sopine-baseboard -- 2.28.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201210084232.1913871-1-icenowy%40aosc.io.
[linux-sunxi] [PATCH 0/3] PineTab with new panel DT
As discussed on the mailing list, here introduces a new DT for new PineTabs. Icenowy Zheng (3): dt-bindings: arm: sunxi: add PineTab new panel DT binding arm64: allwinner: dts: a64: add DT for PineTab with new LCD panel dt-bindings: arm: sunxi: note that old PineTab compatible has old panel .../devicetree/bindings/arm/sunxi.yaml| 7 - arch/arm64/boot/dts/allwinner/Makefile| 1 + .../sun50i-a64-pinetab-new-panel.dts | 26 +++ 3 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-new-panel.dts -- 2.28.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201210083722.1912981-1-icenowy%40aosc.io.
