Hi Samuel,
On Sun, Jan 03, 2021 at 04:54:46AM -0600, Samuel Holland wrote:
> From: Ondrej Jirman
>
> Allow the driver to wake up the system on key press. Since using the
> LRADC as a wakeup source requires keeping on an additional power domain,
> disable the wakeup source by default.
Why isn't
On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> While currently none of the newer Allwinner SoCs currently has I2C
> support implemented in U-Boot, this will change soon. mvtwsi driver is
> good as it is for them except one macro. Update it to be ready once I2C
> support lands for those SoCs.
>
>
On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> It turns out that there are at least 2 other SoCs which have basically
> the same memory map, similar clocks and other features as H6. It's very
> likely that we'll see more such SoCs in the future. In order to ease
> porting to new SoCs and lower ifdef
This is just refreshed v4 from here:
https://patchwork.ozlabs.org/project/uboot/list/?series=156657=*
Patches are only rebased, DT updated and defconfig regenerated, so
I kept old tags. Only difference with old version is that this one
does not sync H6 DT files. Becasue of that, this series
From: Andre Heider
Refactor setup_environment() so we can use the created sid for a
Bluetooth address too.
Signed-off-by: Andre Heider
Acked-by: Maxime Ripard
[rebased]
Signed-off-by: Jernej Skrabec
---
board/sunxi/board.c | 121
1 file changed,
From: Andre Heider
Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3,
ship with the controller default address.
Add a config option to fix it up so it can function properly.
Signed-off-by: Andre Heider
Tested-by: Ondrej Jirman
Acked-by: Maxime Ripard
[rebased]
Signed-off-by:
From: Andre Heider
dts file is taken from Linux 5.11-rc1 tag.
The Bluetooth controller of this device ships with a default address,
use the new CONFIG_FIXUP_BDADDR option to fix it up.
Signed-off-by: Andre Heider
Acked-by: Maxime Ripard
[Updated OrangePi 3 DT, rebase and config update]
On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> There was no need to have prcm definitions for H6 and similar SoCs till
> now. However, support R_I2C will be needed soon in SPL.
>
> Move old definitions to prcm_sun6i.h and add new ones in prcm_sun50i.h.
> One of those files will be selected in common
On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> I2C support, especially R_I2C port, will be needed in future. Upcoming
> support for H616 will need R_I2C to adjust DRAM voltage.
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Samuel Holland
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On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> This port is needed for communication with PMIC. SPL uses it to set DRAM
> voltage on H616 boards.
>
> Signed-off-by: Jernej Skrabec
> ---
> arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
> board/sunxi/board.c| 4
> 2 files
On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> This port is used for debug terminal on all known H616 boards.
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Samuel Holland
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On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> From: Andre Przywara
>
> H616 supports and needs bigger SPL than 32 KiB, mostly due to big DRAM
> driver and need for PMIC configuration, which pull several drivers which
> are not needed otherwise.
>
> Signed-off-by: Andre Przywara
> Signed-off-by:
On 1.01.2021 13:52, Paolo Cremonese wrote:
> Hi All,
> I need to use ADC0 of A20 using kernel 5.8
> With old kernels (3.4) I had to add sun4i-keyboard module.
> In new kernels, I have seen that the device tree has a node called lradc
> which should load the driver sun4i-lradc-keys
>
> The driver
On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> Allwinner H616 supports many types of DRAM. Most notably it supports
> LPDDR4. However, all commercially available boards at this time use
> only DDR3, so this commit adds only DDR3 support.
>
> Controller and MBUS are very similar to H6 but PHY is
On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> H616 has mostly the same clocks as H6 with some small differences. Just
> reuse H6 clocks for H616 and handle differences with macros.
>
> Signed-off-by: Jernej Skrabec
> ---
> .../include/asm/arch-sunxi/clock_sun50i_h6.h | 18 +-
>
On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> H616 is very similar to H6 so most of the infrastructure can be reused.
> However, two big differences are that it doesn't have functional SRAM A2
> which is usually used for TF-A and it doesn't have ARISC co-processor.
> It also needs bigger SPL size -
Hello Jernej,
Am 03.01.21 um 10:26 schrieb Jernej Skrabec:
> While currently none of the newer Allwinner SoCs currently has I2C
> support implemented in U-Boot, this will change soon. mvtwsi driver is
> good as it is for them except one macro. Update it to be ready once I2C
> support lands for
This series introduces Tanix TX6 TV box support based on Allwinner H6
SoC. First patch syncs H6 DT files from Linux 5.11-rc1 release and
second one adds support for Tanix TX6 board.
Please take a look.
Best regards,
Jernej
Changes from v1:
- add missing tanix_tx6_defconfig
Jernej Skrabec (2):
This commit adds support for Tanix TX6 TV box, based on H6. It's low end
H6 board, with 3 GiB of RAM, eMMC, fast ethernet, USB, IR and other
peripherals.
DT file is taken from Linux 5.11-rc1 release.
Signed-off-by: Jernej Skrabec
---
arch/arm/dts/Makefile| 3 +-
Updated H6 DT files are based on Linux 5.11-rc1 release.
Signed-off-by: Jernej Skrabec
---
arch/arm/dts/sun50i-h6-beelink-gs1.dts| 70 +++-
arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 117 +++
arch/arm/dts/sun50i-h6-orangepi-lite2.dts | 71 +++-
arch/arm/dts/sun50i-h6-orangepi.dtsi
As there is an RSB controller in the H6 SoC, there should be some pin
configuration for it. While no such configuration is documented, the
"s_i2c" pins are suspiciously on the "alternate" function 3, with no
primary function 2 given. This suggests the primary function for these
pins is actually
While no information about the H6 RSB controller is included in the
datasheet or manual, the vendor BSP and power management blob both
reference the RSB clock parent and register address. These values were
verified by experimentation.
Since this clock/reset are added late, the specifier is added
The H6 SoC contains an undocumented but fully functional RSB controller.
Add support for it. The MMIO register address matches other SoCs of the
same generation, and the IRQ matches a hole in the documented IRQ list.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
On boards where the only peripheral connected to PL0/PL1 is an X-Powers
PMIC, configure the connection to use the RSB bus rather than the I2C
bus. Compared to the I2C controller that shares the pins, the RSB
controller allows a higher bus frequency, and it is more CPU-efficient.
Signed-off-by:
The Allwinner H6 SoC contains an RSB controller. It is almost completely
undocumented, so it was missed when doing the initial SoC bringup.
This series adds the clock/reset, pin configuration, and device tree
node needed to use the RSB controller. Since RSB is faster, simpler, and
generally more
Maintain bitmaps of wake-enabled IRQs and mux inputs, and program them
to the hardware during the syscore phase of suspend and shutdown. Then
restore the original set of enabled IRQs (only the NMI) during resume.
This serves two purposes. First, it lets power management firmware
running on the
Allwinner sun6i/sun8i/sun50i SoCs (A31 and newer) have two interrupt
controllers: GIC and R_INTC. GIC does not support wakeup. R_INTC handles
the external NMI pin, and provides 32+ IRQs to the ARISC. The first 16
of these correspond 1:1 to a block of GIC IRQs starting with the NMI.
The last 13-16
The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
original sun4i interrupt controller than the sun7i/sun9i NMI controller.
It is used for two distinct purposes:
- To control the trigger, latch, and mask for the NMI input pin
- To provide the interrupt input for the ARISC
The R_INTC block controls more than just the NMI, and it is a different
hardware block than the NMI INTC found in some other Allwinner SoCs, so
the label "nmi_intc" is inaccurate. Name it "r_intc" to match the
compatible and to match the few references in the vendor documentation.
Signed-off-by:
The binding of R_INTC was updated to allow specifying interrupts other
than the external NMI, since routing those interrupts through the R_INTC
driver allows using them for wakeup.
Update the device trees to use the new binding.
Signed-off-by: Samuel Holland
---
The H3 and H5 SoCs have an additional interrupt controller in the RTC
power domain that can be used to enable wakeup for certain IRQs.
Add a node for it.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git
All IRQs that can be used to wake up the system must be routed through
r_intc, so they are visible to firmware while the system is suspended.
In addition to the external NMI input, which is already routed through
r_intc, these include PIO and R_PIO (gpio-keys), the LRADC, and the RTC.
The binding of R_INTC was updated to allow specifying interrupts other
than the external NMI, since routing those interrupts through the R_INTC
driver allows using them for wakeup.
Update the device trees to use the new binding.
Signed-off-by: Samuel Holland
---
All IRQs that can be used to wake up the system must be routed through
r_intc, so they are visible to firmware while the system is suspended.
In addition to the external NMI input, which is already routed through
r_intc, these include PIO and R_PIO (gpio-keys), the LRADC, and the RTC.
The Allwinner H3 SoC contains an R_INTC that is, as far as we know,
compatible with the R_INTC present in other sun8i/sun50i SoCs starting
with the A31. Since the R_INTC hardware is undocumented, introduce a new
compatible for the R_INTC variant in this SoC, in case there turns out
to be some
The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional
functionality compared to the sun7i/sun9i NMI controller. Among other
things, it multiplexes up to 128 interrupts corresponding to (and in
parallel to) the first 128 GIC SPIs. This means the NMI is no longer the
lowest-numbered
From: Ondrej Jirman
Allow the driver to wake up the system on key press. Since using the
LRADC as a wakeup source requires keeping on an additional power domain,
disable the wakeup source by default.
Signed-off-by: Ondrej Jirman
[Samuel: disable the wakeup source by default]
Signed-off-by:
H616 is very similar to H6 so most of the infrastructure can be reused.
However, two big differences are that it doesn't have functional SRAM A2
which is usually used for TF-A and it doesn't have ARISC co-processor.
It also needs bigger SPL size - 48 KiB.
Signed-off-by: Jernej Skrabec
---
From: Andre Przywara
---
drivers/net/sun8i_emac.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 4524604126c9..7e57f1d01c8c 100644
--- a/drivers/net/sun8i_emac.c
+++
Allwinner H616 supports many types of DRAM. Most notably it supports
LPDDR4. However, all commercially available boards at this time use
only DDR3, so this commit adds only DDR3 support.
Controller and MBUS are very similar to H6 but PHY is completely
unknown.
Signed-off-by: Jernej Skrabec
---
This commit introduces H616 DTSI file and dt-bindings headers needed for
device tree files.
Files are taken from initial Linux H616 support submission with minor
change - emac0 fallback has H6 compatible instead of A64, otherwise
network doesn't work. H616 DTSI is not merged upstream yet.
H616 pinctrl is no different configuration wise than others, so just add
compatible for it.
Signed-off-by: Jernej Skrabec
---
drivers/gpio/sunxi_gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 02c3471b5684..1985ee5d2fc9
This commit introduces DM H616 clock driver.
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi/Kconfig| 7 ++
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_h616.c | 120 +++
3 files changed, 128 insertions(+)
create mode 100644
There was no need to have prcm definitions for H6 and similar SoCs till
now. However, support R_I2C will be needed soon in SPL.
Move old definitions to prcm_sun6i.h and add new ones in prcm_sun50i.h.
One of those files will be selected in common prcm.h based on defined
macros.
This commit
I2C support, especially R_I2C port, will be needed in future. Upcoming
support for H616 will need R_I2C to adjust DRAM voltage.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/clock_sun50i_h6.h | 1 +
arch/arm/mach-sunxi/Kconfig | 2 +-
From: Andre Przywara
H616 supports and needs bigger SPL than 32 KiB, mostly due to big DRAM
driver and need for PMIC configuration, which pull several drivers which
are not needed otherwise.
Signed-off-by: Andre Przywara
Signed-off-by: Jernej Skrabec
---
arch/arm/mach-sunxi/board.c | 12
H616 has mostly the same clocks as H6 with some small differences. Just
reuse H6 clocks for H616 and handle differences with macros.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/clock_sun50i_h6.h | 18 +-
arch/arm/mach-sunxi/clock_sun50i_h6.c | 10
It turns out that several SoCs share same mmc configuration as H6. In
order to lower ifdef clutter replace H6 specific macro with common one.
Signed-off-by: Jernej Skrabec
---
arch/arm/include/asm/arch-sunxi/mmc.h | 2 +-
drivers/mmc/sunxi_mmc.c | 12 ++--
2 files
While currently none of the newer Allwinner SoCs currently has I2C
support implemented in U-Boot, this will change soon. mvtwsi driver is
good as it is for them except one macro. Update it to be ready once I2C
support lands for those SoCs.
Signed-off-by: Jernej Skrabec
---
drivers/i2c/mvtwsi.c
This port is used for debug terminal on all known H616 boards.
Signed-off-by: Jernej Skrabec
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
arch/arm/mach-sunxi/board.c| 4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
This port is needed for communication with PMIC. SPL uses it to set DRAM
voltage on H616 boards.
Signed-off-by: Jernej Skrabec
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
board/sunxi/board.c| 4
2 files changed, 5 insertions(+)
diff --git
OrangePi Zero2 is SBC based on Allwinner H616 with 1 GiB of RAM, SD card
support, gigabit ethernet, micro HDMI, WIFI, Bluetooth and 1 USB 2.0
port. It also has two GPIO headers which allows further peripherals to
be used.
Device Tree file is taken from initial OrangePi Zero2 Linux submission
and
Dne nedelja, 03. januar 2021 ob 10:56:52 CET je Jernej Skrabec napisal(a):
> This series introduces Tanix TX6 TV box support based on Allwinner H6
> SoC. First patch syncs H6 DT files from Linux 5.11-rc1 release and
> second one adds support for Tanix TX6 board.
>
> Please take a look.
>
> Best
To save power, gate the clock when the bus is inactive, during system
sleep, and during shutdown. On some platforms, specifically Allwinner
A13/A20, gating the clock implicitly resets the module as well. Since
the module already needs to be reset after some suspend/resume cycles,
it is simple
This series introduces H616 support. Later patches add also OrangePi
Zero2 support but since H616 DT is not merged into Linux yet, I don't
expect them to land yet.
Patches 1-13 are ready to land, while 14-17 depends on non-upstreamed
DT yet.
This work relies on
This PMIC can be found on H616 boards and it's very similar to AXP805
and AXP806.
Signed-off-by: Jernej Skrabec
---
arch/arm/mach-sunxi/pmic_bus.c | 6 +++
board/sunxi/board.c| 10 +++--
drivers/power/Kconfig | 13 +-
drivers/power/Makefile | 1 +
It turns out that there are at least 2 other SoCs which have basically
the same memory map, similar clocks and other features as H6. It's very
likely that we'll see more such SoCs in the future. In order to ease
porting to new SoCs and lower ifdef clutter, introduce common symbol for
them.
This commit adds support for Tanix TX6 TV box, based on H6. It's low end
H6 board, with 3 GiB of RAM, eMMC, fast ethernet, USB, IR and other
peripherals.
DT file is taken from Linux 5.11-rc1 release.
Signed-off-by: Jernej Skrabec
---
arch/arm/dts/Makefile| 3 +-
Updated H6 DT files are based on Linux 5.11-rc1 release.
Signed-off-by: Jernej Skrabec
---
arch/arm/dts/sun50i-h6-beelink-gs1.dts| 70 +++-
arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 117 +++
arch/arm/dts/sun50i-h6-orangepi-lite2.dts | 71 +++-
arch/arm/dts/sun50i-h6-orangepi.dtsi
On Sun, Jan 3, 2021 at 6:00 PM Samuel Holland wrote:
>
> As there is an RSB controller in the H6 SoC, there should be some pin
> configuration for it. While no such configuration is documented, the
> "s_i2c" pins are suspiciously on the "alternate" function 3, with no
> primary function 2 given.
While stmmac_pltfr_remove calls sun8i_dwmac_exit, the sun8i_dwmac_init
and sun8i_dwmac_exit functions are also called by the stmmac_platform
suspend/resume callbacks. They may be called many times during the
device's lifetime and should not release resources used by the driver.
Furthermore, there
This series fixes issues preventing dwmac-sun8i from working after a
suspend/resume cycle. Those issues include the PHY being left powered
off, the MAC syscon configuration being reset, and the reference to the
reset controller being improperly dropped. They also fix related issues
in probe error
sun8i_dwmac_exit calls sun8i_dwmac_unpower_internal_phy, but
sun8i_dwmac_init did not call sun8i_dwmac_power_internal_phy. This
caused PHY power to remain off after a suspend/resume cycle. Fix this by
recording if PHY power should be restored, and if so, restoring it.
Fixes: 634db83b8265 ("net:
stmmac_pltfr_remove does three things in one function, making it
inapproprate for unwinding the steps in the probe function. Currently,
a failure before the call to stmmac_dvr_probe would leak OF node
references due to missing a call to stmmac_remove_config_dt. And an
error in stmmac_dvr_probe
Previously, sun8i_dwmac_set_syscon was called from a chain of functions
in several different files:
sun8i_dwmac_probe
stmmac_dvr_probe
stmmac_hw_init
stmmac_hwif_init
sun8i_dwmac_setup
sun8i_dwmac_set_syscon
which made the lifetime of the
This is a deinitialization function that always returned zero, and that
return value was always ignored. Have it return void instead.
Signed-off-by: Samuel Holland
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
Adjust the spacing and use an explicit "return 0" in the success path
to make the function easier to parse.
Signed-off-by: Samuel Holland
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Use the appropriate function instead of reimplementing it,
and update the error message to match the code.
Signed-off-by: Samuel Holland
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
These patches clean up some things I noticed while fixing suspend/resume
behavior. The first four are minor code improvements. The last one adds
a shutdown hook to minimize power consumption on boards without a PMIC.
Samuel Holland (5):
net: stmmac: dwmac-sun8i: Return void from PHY unpower
The Ethernet MAC and PHY are usually major consumers of power on boards
which may not be able to fully power off (that have no PMIC). Powering
down the MAC and internal PHY saves power while these boards are "off".
Signed-off-by: Samuel Holland
---
sun8i_dwmac_unpower_internal_phy already checks if the PHY is powered,
so there is no need to do it again here.
Signed-off-by: Samuel Holland
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
Since system firmware is likely to use the RSB bus to communicate with a
PMIC while the system is suspended, we cannot make any assumptions about
the controller state after resuming. Thus it is important to completely
reinitialize the controller.
The RSB bus needs to be ready as soon as IRQs are
This series adds system (complete power down) and runtime (clock gate)
PM hooks to the RSB controller driver. Tested on A64 and H6.
Samuel Holland (4):
bus: sunxi-rsb: Move OF match table
bus: sunxi-rsb: Split out controller init/exit functions
bus: sunxi-rsb: Implement
For some reason, this driver's OF match table was placed above the
probe/remove functions, far away from the platform_driver definition.
Adding device PM ops would move the table even farther away. Let's move
it to the usual place, right before the platform_driver.
Signed-off-by: Samuel Holland
Gate the clock to save power while the controller is idle.
Signed-off-by: Samuel Holland
---
drivers/bus/sunxi-rsb.c | 44 +
1 file changed, 44 insertions(+)
diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c
index efd222f36cdc..ba5100dfc413
This separates the resource acquisition from the hardware initialization
phase, so the hardware initialization can be repeated after system
suspend/resume. The same is done for the exit/remove function, except
that there is no resource deallocation phase due to the use of devres.
The requested
On 1/3/21 5:27 AM, Marc Zyngier wrote:
> On Sun, 03 Jan 2021 10:30:54 +,
> Samuel Holland wrote:
>>
>> The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
>> original sun4i interrupt controller than the sun7i/sun9i NMI controller.
>> It is used for two distinct purposes:
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