Re: [linux-sunxi] LRADC on A20
On 4.01.2021 18:16, Ing. Paolo Cremonese wrote: > Hello Gediz, > thank you for your kind reply. > in attachment the files describing the device tree. > lradc is noted in the .dtsi and is disabled for default: to enable it > I'm using the overlay lradc_enable.dtbo (the source is lradc-enable.dts) > the dmesg and lsmod outputs are in the related .txt > Thank you again for your time. > Best regards, > Paolo Cremonese You're welcome. I did not see any obvious warning/error in dmesg output. I'm not very familiar with DTBO files but compared "lradc-enable.dts" to valid ones and it looks okay. But I'd still somehow check if overlay is recognized/loaded properly. That's not your case but, even if module is built in to the kernel, it obviously does not start with a missing lradc node. I've set LRADC node status to "disabled" in the DTS to test it and there were no complaints about LRADC in the dmesg. Of course, I could not see the device under "/dev/input/eventX" anymore using "evtest" after disabling it. If you have compiled the kernel yourself, I'd recommend to check if CONFIG_KEYBOARD_SUN4I_LRADC is enabled. Otherwise, looking at "/proc/configz.gz" may help. I've tested the following on my device which has an A13. Their LRADC is probably identical. Maybe the output may help as a reference. # grep lradc /lib/modules/5.10.1/modules.builtin kernel/drivers/input/keyboard/sun4i-lradc-keys.ko # dmesg | grep lradc [1.597213] input: 1c22800.lradc as /devices/platform/soc/1c22800.lradc/input/input0 Regards, Gediz -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/f9d9406e3e7b4c74819adfc2d97b7927%40genemek.com.
[linux-sunxi] Re: [PATCH v2 4/4] arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection
On 1/4/21 4:54 AM, André Przywara wrote:
> On 03/01/2021 10:00, Samuel Holland wrote:
>> On boards where the only peripheral connected to PL0/PL1 is an X-Powers
>> PMIC, configure the connection to use the RSB bus rather than the I2C
>> bus. Compared to the I2C controller that shares the pins, the RSB
>> controller allows a higher bus frequency, and it is more CPU-efficient.
>
> But is it really necessary to change the DTs for those boards in this
> way? It means those newer DTs now become incompatible with older
> kernels, and I don't know if those reasons above really justify this.
>
> I understand that we officially don't care about "newer DTs on older
> kernels", but do we really need to break this deliberately, for no
> pressing reasons?
That's a reasonable concern. I am fine if you want to delay or drop patch 4.
Cheers,
Samuel
> Cheers,
> Andre
>
> P.S. I am fine with supporting RSB on H6, and even using it on new DTs,
> just want to avoid breaking existing ones.
>
>> Signed-off-by: Samuel Holland
>> ---
>> .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 38 +--
>> .../dts/allwinner/sun50i-h6-orangepi-3.dts| 14 +++
>> .../dts/allwinner/sun50i-h6-orangepi.dtsi | 22 +--
>> 3 files changed, 37 insertions(+), 37 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
>> b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
>> index 7c9dbde645b5..3452add30cc4 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
>> @@ -150,12 +150,28 @@ {
>> vcc-pg-supply = <_aldo1>;
>> };
>>
>> -_i2c {
>> +_ir {
>> +linux,rc-map-name = "rc-beelink-gs1";
>> +status = "okay";
>> +};
>> +
>> +_pio {
>> +/*
>> + * FIXME: We can't add that supply for now since it would
>> + * create a circular dependency between pinctrl, the regulator
>> + * and the RSB Bus.
>> + *
>> + * vcc-pl-supply = <_aldo1>;
>> + */
>> +vcc-pm-supply = <_aldo1>;
>> +};
>> +
>> +_rsb {
>> status = "okay";
>>
>> -axp805: pmic@36 {
>> +axp805: pmic@745 {
>> compatible = "x-powers,axp805", "x-powers,axp806";
>> -reg = <0x36>;
>> +reg = <0x745>;
>> interrupt-parent = <_intc>;
>> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>> interrupt-controller;
>> @@ -273,22 +289,6 @@ sw {
>> };
>> };
>>
>> -_ir {
>> -linux,rc-map-name = "rc-beelink-gs1";
>> -status = "okay";
>> -};
>> -
>> -_pio {
>> -/*
>> - * PL0 and PL1 are used for PMIC I2C
>> - * don't enable the pl-supply else
>> - * it will fail at boot
>> - *
>> - * vcc-pl-supply = <_aldo1>;
>> - */
>> -vcc-pm-supply = <_aldo1>;
>> -};
>> -
>> {
>> clocks = <_osc32k>;
>> };
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
>> b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
>> index 15c9dd8c4479..16702293ac0b 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
>> @@ -175,12 +175,16 @@ {
>> vcc-pg-supply = <_vcc_wifi_io>;
>> };
>>
>> -_i2c {
>> +_ir {
>> +status = "okay";
>> +};
>> +
>> +_rsb {
>> status = "okay";
>>
>> -axp805: pmic@36 {
>> +axp805: pmic@745 {
>> compatible = "x-powers,axp805", "x-powers,axp806";
>> -reg = <0x36>;
>> +reg = <0x745>;
>> interrupt-parent = <_intc>;
>> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>> interrupt-controller;
>> @@ -291,10 +295,6 @@ sw {
>> };
>> };
>>
>> -_ir {
>> -status = "okay";
>> -};
>> -
>> {
>> clocks = <_osc32k>;
>> };
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
>> index ebc120a9232f..23e3cb2ffd8d 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
>> @@ -112,12 +112,20 @@ {
>> vcc-pg-supply = <_aldo1>;
>> };
>>
>> -_i2c {
>> +_ir {
>> +status = "okay";
>> +};
>> +
>> +_pio {
>> +vcc-pm-supply = <_bldo3>;
>> +};
>> +
>> +_rsb {
>> status = "okay";
>>
>> -axp805: pmic@36 {
>> +axp805: pmic@745 {
>> compatible = "x-powers,axp805", "x-powers,axp806";
>> -reg = <0x36>;
>> +reg = <0x745>;
>> interrupt-parent = <_intc>;
>> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>> interrupt-controller;
>> @@ -232,14 +240,6 @@ sw {
>> };
>> };
>>
>> -_ir {
>> -status = "okay";
>> -};
>> -
>> -_pio {
>> -vcc-pm-supply = <_bldo3>;
>> -};
>> -
>> {
>> clocks = <_osc32k>;
>> };
>>
>
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop
Re: [linux-sunxi] [PATCH 11/17] sunxi: Add H616 DRAM support
On 1/4/21 12:39 PM, Jernej Škrabec wrote:
> Dne ponedeljek, 04. januar 2021 ob 03:39:52 CET je Samuel Holland napisal(a):
>> On 1/3/21 3:26 AM, Jernej Skrabec wrote:
>>> Allwinner H616 supports many types of DRAM. Most notably it supports
>>> LPDDR4. However, all commercially available boards at this time use
>>> only DDR3, so this commit adds only DDR3 support.
>>>
>>> Controller and MBUS are very similar to H6 but PHY is completely
>>> unknown.
>>>
>>> Signed-off-by: Jernej Skrabec
>>> ---
>>>
>>> arch/arm/include/asm/arch-sunxi/dram.h|2 +
>>> .../include/asm/arch-sunxi/dram_sun50i_h616.h | 159 +++
>>> arch/arm/mach-sunxi/Kconfig | 43 +
>>> arch/arm/mach-sunxi/Makefile |2 +
>>> arch/arm/mach-sunxi/dram_sun50i_h616.c| 1023 +
>>> arch/arm/mach-sunxi/dram_timings/Makefile |2 +
>>> .../mach-sunxi/dram_timings/h616_ddr3_1333.c | 94 ++
>>> 7 files changed, 1325 insertions(+)
>>> create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
>>> create mode 100644 arch/arm/mach-sunxi/dram_sun50i_h616.c
>>> create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
>>>
>>> diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
>>> b/arch/arm/include/asm/arch-sunxi/dram.h index 8002b7efdc19..c3b3e1f512b2
>>> 100644
>>> --- a/arch/arm/include/asm/arch-sunxi/dram.h
>>> +++ b/arch/arm/include/asm/arch-sunxi/dram.h
>>> @@ -29,6 +29,8 @@
>>>
>>> #include
>>> #elif defined(CONFIG_MACH_SUN50I_H6)
>>> #include
>>>
>>> +#elif defined(CONFIG_MACH_SUN50I_H616)
>>> +#include
>>>
>>> #else
>>> #include
>>> #endif
>>>
>>> diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
>>> b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h new file mode 100644
>>> index ..5d105afd6110
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
>>> @@ -0,0 +1,159 @@
>>> +/*
>>> + * H616 dram controller register and constant defines
>>> + *
>>> + * (C) Copyright 2020 Jernej Skrabec
>>> + *
>>> + * Based on H6 one, which is:
>>> + * (C) Copyright 2017 Icenowy Zheng
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +#ifndef _SUNXI_DRAM_SUN50I_H616_H
>>> +#define _SUNXI_DRAM_SUN50I_H616_H
>>> +
>>> +#include
>>> +#ifndef __ASSEMBLY__
>>> +#include
>>> +#endif
>>> +
>>> +enum sunxi_dram_type {
>>> + SUNXI_DRAM_TYPE_DDR3 = 3,
>>> + SUNXI_DRAM_TYPE_DDR4,
>>> + SUNXI_DRAM_TYPE_LPDDR3 = 7,
>>> + SUNXI_DRAM_TYPE_LPDDR4
>>> +};
>>> +
>>> +/* MBUS part is largely the same as in H6, except for one special
>>> register */ +struct sunxi_mctl_com_reg {
>>> + u32 cr; /* 0x000 control register */
>>> + u8 reserved_0x004[4]; /* 0x004 */
>>> + u32 unk_0x008; /* 0x008 */
>>> + u32 tmr;/* 0x00c timer register */
>>> + u8 reserved_0x010[4]; /* 0x010 */
>>> + u32 unk_0x014; /* 0x014 */
>>> + u8 reserved_0x018[8]; /* 0x018 */
>>> + u32 maer0; /* 0x020 master enable register 0 */
>>> + u32 maer1; /* 0x024 master enable register 1 */
>>> + u32 maer2; /* 0x028 master enable register 2 */
>>> + u8 reserved_0x02c[468]; /* 0x02c */
>>> + u32 bwcr; /* 0x200 bandwidth control register */
>>> + u8 reserved_0x204[12]; /* 0x204 */
>>> + /*
>>> +* The last master configured by BSP libdram is at 0x49x, so the
>>> +* size of this struct array is set to 41 (0x29) now.
>>> +*/
>>> + struct {
>>> + u32 cfg0; /* 0x0 */
>>> + u32 cfg1; /* 0x4 */
>>> + u8 reserved_0x8[8]; /* 0x8 */
>>> + } master[41]; /* 0x210 + index * 0x10 */
>>> + u8 reserved_0x4a0[96]; /* 0x4a0 */
>>> + u32 unk_0x500; /* 0x500 */
>>> +};
>>> +check_member(sunxi_mctl_com_reg, unk_0x500, 0x500);
>>> +
>>> +/*
>>> + * Controller registers seems to be the same or at least very similar
>>> + * to those in H6.
>>> + */
>>> +struct sunxi_mctl_ctl_reg {
>>> + u32 mstr; /* 0x000 */
>>> + u32 statr; /* 0x004 unused */
>>> + u32 mstr1; /* 0x008 unused */
>>> + u32 unk_0x00c; /* 0x00c */
>>
>> This is clken (and the same on H6). It is obvious when looking at the
>> standby power-down sequence.
>
> Where is that sequence? I mostly consulted H6 and Zynq docs where this
> register is not explained. I'll update it in next revision.
This is from the H6 ARISC firmware, which has a similar structure to earlier
generations with known registers.
Cheers,
Samuel
> Best regards,
> Jernej
>
>>
>>> + u32 mrctrl0;/* 0x010 unused */
>>> + u32 mrctrl1;/* 0x014 unused */
>>> + u32 mrstatr;/* 0x018 unused */
>>> + u32 mrctrl2;/* 0x01c unused */
>>> + u32 derateen; /* 0x020 unused */
>>> + u32 derateint; /* 0x024 unused */
>>> + u8 reserved_0x028[8]; /* 0x028
Re: [linux-sunxi] [PATCH 12/17] sunxi: Add support for H616 SoC
Dne ponedeljek, 04. januar 2021 ob 03:47:06 CET je Samuel Holland napisal(a):
> On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> > H616 is very similar to H6 so most of the infrastructure can be reused.
> > However, two big differences are that it doesn't have functional SRAM A2
> > which is usually used for TF-A and it doesn't have ARISC co-processor.
> > It also needs bigger SPL size - 48 KiB.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
> > arch/arm/dts/sunxi-u-boot.dtsi | 9 +
> > arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 7 +++
> > arch/arm/mach-sunxi/Kconfig | 11 ++-
> > arch/arm/mach-sunxi/cpu_info.c | 2 ++
> > drivers/power/Kconfig | 1 +
> > include/configs/sunxi-common.h | 10 ++
> > 6 files changed, 39 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/dts/sunxi-u-boot.dtsi
> > b/arch/arm/dts/sunxi-u-boot.dtsi index c77cf7cacf0c..7e8644f390a8 100644
> > --- a/arch/arm/dts/sunxi-u-boot.dtsi
> > +++ b/arch/arm/dts/sunxi-u-boot.dtsi
> > @@ -3,6 +3,9 @@
> >
> > #ifdef CONFIG_MACH_SUN50I_H6
> > #define BL31_ADDR 0x104000
> > #define SCP_ADDR 0x114000
> >
> > +#elif defined(CONFIG_MACH_SUN50I_H616)
> > +#define BL31_ADDR 0x40004000
> > +#define SCP_ADDR 0x028000
>
> There should be no SCP_ADDR if there is no SCP firmware.
Nice catch!
>
> > #else
> > #define BL31_ADDR 0x44000
> > #define SCP_ADDR 0x5
> >
> > @@ -61,6 +64,7 @@
> >
> > };
> >
> > };
> >
> > +#ifndef CONFIG_MACH_SUN50I_H616
> >
> > scp {
> >
> > description = "SCP
firmware";
> > type = "firmware";
> >
> > @@ -73,6 +77,7 @@
> >
> > missing-msg
= "scp-sunxi";
> >
> > };
> >
> > };
> >
> > +#endif
> >
> > @fdt-SEQ {
> >
> > description = "NAME";
> >
> > @@ -87,7 +92,11 @@
> >
> > @config-SEQ {
> >
> > description = "NAME";
> > firmware = "atf";
> >
> > +#ifdef CONFIG_MACH_SUN50I_H616
> > + loadables = "uboot";
> > +#else
> >
> > loadables = "scp",
"uboot";
> >
> > +#endif
> >
> > fdt = "fdt-SEQ";
> >
> > };
> >
> > };
> >
> > diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> > b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index
> > 6392cb07b472..d9cf8ae04288 100644
> > --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> > +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> > @@ -28,13 +28,20 @@
> >
> > #define SUNXI_GIC400_BASE 0x0302
> > #define SUNXI_IOMMU_BASE 0x030F
> >
> > +#ifdef CONFIG_MACH_SUN50I_H6
> >
> > #define SUNXI_DRAM_COM_BASE0x04002000
> > #define SUNXI_DRAM_CTL0_BASE 0x04003000
> > #define SUNXI_DRAM_PHY0_BASE 0x04005000
> >
> > +#endif
> >
> > #define SUNXI_NFC_BASE 0x04011000
> > #define SUNXI_MMC0_BASE0x0402
> > #define SUNXI_MMC1_BASE0x04021000
> > #define SUNXI_MMC2_BASE0x04022000
> >
> > +#ifdef CONFIG_MACH_SUN50I_H616
> > +#define SUNXI_DRAM_COM_BASE0x047FA000
> > +#define SUNXI_DRAM_CTL0_BASE 0x047FB000
> > +#define SUNXI_DRAM_PHY0_BASE 0x0480
> > +#endif
> >
> > #define SUNXI_UART0_BASE 0x0500
> > #define SUNXI_UART1_BASE 0x05000400
> >
> > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > index 1a5497989f04..859b30d74ceb 100644
> > --- a/arch/arm/mach-sunxi/Kconfig
> > +++ b/arch/arm/mach-sunxi/Kconfig
> > @@ -190,9 +190,10 @@ config MACH_SUNXI_H3_H5
> >
> > select SUPPORT_SPL
> >
> > # TODO: try out A80's 8GiB DRAM space
> >
> > +# TODO: H616 supports 4 GiB DRAM space
> >
> > config SUNXI_DRAM_MAX_SIZE
> >
> > hex
> >
> > - default 0xC000 if MACH_SUN50I || MACH_SUN50I_H5 ||
MACH_SUN50I_H6
> > + default 0xC000 if MACH_SUN50I || MACH_SUN50I_H5 ||
MACH_SUN50I_H6 ||
> > MACH_SUN50I_H616>
> > default 0x8000
> >
> > choice
> >
> > @@ -354,6 +355,12 @@ config MACH_SUN50I_H6
> >
> > select PHY_SUN4I_USB
> > select DRAM_SUN50I_H6
> >
> > +config MACH_SUN50I_H616
> > + bool "sun50i
Re: [linux-sunxi] [PATCH 11/17] sunxi: Add H616 DRAM support
Dne ponedeljek, 04. januar 2021 ob 03:39:52 CET je Samuel Holland napisal(a):
> On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> > Allwinner H616 supports many types of DRAM. Most notably it supports
> > LPDDR4. However, all commercially available boards at this time use
> > only DDR3, so this commit adds only DDR3 support.
> >
> > Controller and MBUS are very similar to H6 but PHY is completely
> > unknown.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
> > arch/arm/include/asm/arch-sunxi/dram.h|2 +
> > .../include/asm/arch-sunxi/dram_sun50i_h616.h | 159 +++
> > arch/arm/mach-sunxi/Kconfig | 43 +
> > arch/arm/mach-sunxi/Makefile |2 +
> > arch/arm/mach-sunxi/dram_sun50i_h616.c| 1023 +
> > arch/arm/mach-sunxi/dram_timings/Makefile |2 +
> > .../mach-sunxi/dram_timings/h616_ddr3_1333.c | 94 ++
> > 7 files changed, 1325 insertions(+)
> > create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> > create mode 100644 arch/arm/mach-sunxi/dram_sun50i_h616.c
> > create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
> >
> > diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
> > b/arch/arm/include/asm/arch-sunxi/dram.h index 8002b7efdc19..c3b3e1f512b2
> > 100644
> > --- a/arch/arm/include/asm/arch-sunxi/dram.h
> > +++ b/arch/arm/include/asm/arch-sunxi/dram.h
> > @@ -29,6 +29,8 @@
> >
> > #include
> > #elif defined(CONFIG_MACH_SUN50I_H6)
> > #include
> >
> > +#elif defined(CONFIG_MACH_SUN50I_H616)
> > +#include
> >
> > #else
> > #include
> > #endif
> >
> > diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> > b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h new file mode 100644
> > index ..5d105afd6110
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> > @@ -0,0 +1,159 @@
> > +/*
> > + * H616 dram controller register and constant defines
> > + *
> > + * (C) Copyright 2020 Jernej Skrabec
> > + *
> > + * Based on H6 one, which is:
> > + * (C) Copyright 2017 Icenowy Zheng
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#ifndef _SUNXI_DRAM_SUN50I_H616_H
> > +#define _SUNXI_DRAM_SUN50I_H616_H
> > +
> > +#include
> > +#ifndef __ASSEMBLY__
> > +#include
> > +#endif
> > +
> > +enum sunxi_dram_type {
> > + SUNXI_DRAM_TYPE_DDR3 = 3,
> > + SUNXI_DRAM_TYPE_DDR4,
> > + SUNXI_DRAM_TYPE_LPDDR3 = 7,
> > + SUNXI_DRAM_TYPE_LPDDR4
> > +};
> > +
> > +/* MBUS part is largely the same as in H6, except for one special
> > register */ +struct sunxi_mctl_com_reg {
> > + u32 cr; /* 0x000 control register */
> > + u8 reserved_0x004[4]; /* 0x004 */
> > + u32 unk_0x008; /* 0x008 */
> > + u32 tmr;/* 0x00c timer register */
> > + u8 reserved_0x010[4]; /* 0x010 */
> > + u32 unk_0x014; /* 0x014 */
> > + u8 reserved_0x018[8]; /* 0x018 */
> > + u32 maer0; /* 0x020 master enable register 0 */
> > + u32 maer1; /* 0x024 master enable register 1 */
> > + u32 maer2; /* 0x028 master enable register 2 */
> > + u8 reserved_0x02c[468]; /* 0x02c */
> > + u32 bwcr; /* 0x200 bandwidth control register */
> > + u8 reserved_0x204[12]; /* 0x204 */
> > + /*
> > +* The last master configured by BSP libdram is at 0x49x, so the
> > +* size of this struct array is set to 41 (0x29) now.
> > +*/
> > + struct {
> > + u32 cfg0; /* 0x0 */
> > + u32 cfg1; /* 0x4 */
> > + u8 reserved_0x8[8]; /* 0x8 */
> > + } master[41]; /* 0x210 + index * 0x10 */
> > + u8 reserved_0x4a0[96]; /* 0x4a0 */
> > + u32 unk_0x500; /* 0x500 */
> > +};
> > +check_member(sunxi_mctl_com_reg, unk_0x500, 0x500);
> > +
> > +/*
> > + * Controller registers seems to be the same or at least very similar
> > + * to those in H6.
> > + */
> > +struct sunxi_mctl_ctl_reg {
> > + u32 mstr; /* 0x000 */
> > + u32 statr; /* 0x004 unused */
> > + u32 mstr1; /* 0x008 unused */
> > + u32 unk_0x00c; /* 0x00c */
>
> This is clken (and the same on H6). It is obvious when looking at the
> standby power-down sequence.
Where is that sequence? I mostly consulted H6 and Zynq docs where this
register is not explained. I'll update it in next revision.
Best regards,
Jernej
>
> > + u32 mrctrl0;/* 0x010 unused */
> > + u32 mrctrl1;/* 0x014 unused */
> > + u32 mrstatr;/* 0x018 unused */
> > + u32 mrctrl2;/* 0x01c unused */
> > + u32 derateen; /* 0x020 unused */
> > + u32 derateint; /* 0x024 unused */
> > + u8 reserved_0x028[8]; /* 0x028 */
> > + u32 pwrctl; /* 0x030 unused */
> > + u32 pwrtmg; /* 0x034 unused */
> > + u32 hwlpctl;/* 0x038 unused */
> > + u8
Re: [linux-sunxi] [PATCH 10/17] sunxi: add support for R_I2C on H616
Dne ponedeljek, 04. januar 2021 ob 03:33:12 CET je Samuel Holland napisal(a):
> On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> > This port is needed for communication with PMIC. SPL uses it to set DRAM
> > voltage on H616 boards.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
> > arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
> > board/sunxi/board.c| 4
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
> > b/arch/arm/include/asm/arch-sunxi/gpio.h index cdb7dbd5b8e5..de77bf638e21
> > 100644
> > --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> > @@ -220,6 +220,7 @@ enum sunxi_gpio_number {
> >
> > #define SUN8I_A23_GPL_R_TWI3
> > #define SUN8I_GPL_R_UART 2
> > #define SUN50I_GPL_R_TWI 2
> >
> > +#define SUN50I_H616_GPL_R_TWI 3
>
> The fact that I2C is at function 3 makes me suspicious that there is RSB
> at function 2. Have you checked if that is the case?
BSP Linux pinctrl has function 2 s_rsb0, so yes, that should be the case.
However, it doesn't have RSB DT node anywhere. Datasheet mentions RSB only in
CCU diagram, so no details anywhere. I didn't test it.
Best regards,
Jernej
>
> Either way:
>
> Reviewed-by: Samuel Holland
>
> > #define SUN9I_GPN_R_RSB3
> >
> > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > index 54ff9bc92396..727e8320318f 100644
> > --- a/board/sunxi/board.c
> > +++ b/board/sunxi/board.c
> > @@ -196,6 +196,10 @@ void i2c_init_board(void)
> >
> > clock_twi_onoff(5, 1);
> > sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
> > sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
> >
> > +#elif CONFIG_MACH_SUN50I_H616
> > + clock_twi_onoff(5, 1);
> > + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
> > + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
> >
> > #else
> >
> > clock_twi_onoff(5, 1);
> > sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to linux-sunxi+unsubscr...@googlegroups.com.
To view this discussion on the web, visit
https://groups.google.com/d/msgid/linux-sunxi/4107316.5SLNN0qdvM%40jernej-laptop.
Re: [linux-sunxi] [PATCH 02/17] sunxi: Introduce common symbol for H6 like SoCs
Dne ponedeljek, 04. januar 2021 ob 11:35:41 CET je André Przywara napisal(a):
> On 03/01/2021 23:43, Samuel Holland wrote:
>
> Hi Jernej,
>
> thanks for that patch, that's a nice solution to avoid those long #ifdef
> chains!
>
> > On 1/3/21 3:26 AM, Jernej Skrabec wrote:
> >> It turns out that there are at least 2 other SoCs which have basically
> >> the same memory map, similar clocks and other features as H6. It's very
> >> likely that we'll see more such SoCs in the future. In order to ease
> >> porting to new SoCs and lower ifdef clutter, introduce common symbol for
> >> them.
> >>
> >> Signed-off-by: Jernej Skrabec
> >> ---
> >>
> >> arch/arm/include/asm/arch-sunxi/boot0.h | 2 +-
> >> arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
> >> arch/arm/include/asm/arch-sunxi/cpu.h | 2 +-
> >> arch/arm/include/asm/arch-sunxi/timer.h | 2 +-
> >> arch/arm/mach-sunxi/Kconfig | 21 +
> >> arch/arm/mach-sunxi/Makefile| 2 +-
> >> arch/arm/mach-sunxi/board.c | 4 ++--
> >> arch/arm/mach-sunxi/rmr_switch.S| 2 +-
> >> common/spl/Kconfig | 4 ++--
> >> include/configs/sun50i.h| 2 +-
> >> 10 files changed, 24 insertions(+), 19 deletions(-)
> >>
> >> diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h
> >> b/arch/arm/include/asm/arch-sunxi/boot0.h index
> >> 46d0f0666c2b..e8e8e38f0556 100644
> >> --- a/arch/arm/include/asm/arch-sunxi/boot0.h
> >> +++ b/arch/arm/include/asm/arch-sunxi/boot0.h
> >> @@ -39,7 +39,7 @@
> >>
> >>.word 0xf57ff06f // isb sy
> >>.word 0xe320f003 // wfi
> >>.word 0xeafd // b @wfi
> >>
> >> -#ifndef CONFIG_MACH_SUN50I_H6
> >> +#ifndef CONFIG_SUN50I_GEN_H6
> >>
> >>.word 0x017000a0 // writeable RVBAR mapping address
> >>
> >> #else
> >>
> >>.word 0x09010040 // writeable RVBAR mapping address
> >>
> >> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
> >> b/arch/arm/include/asm/arch-sunxi/clock.h index
> >> 5994130e6b54..cbbe5c7a1e68 100644
> >> --- a/arch/arm/include/asm/arch-sunxi/clock.h
> >> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
> >> @@ -16,7 +16,7 @@
> >>
> >> /* clock control module regs definition */
> >> #if defined(CONFIG_MACH_SUN8I_A83T)
> >> #include
> >>
> >> -#elif defined(CONFIG_MACH_SUN50I_H6)
> >> +#elif defined(CONFIG_SUN50I_GEN_H6)
> >>
> >> #include
> >> #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
> >>
> >>defined(CONFIG_MACH_SUN50I)
> >>
> >> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
> >> b/arch/arm/include/asm/arch-sunxi/cpu.h index 8b57d24e2f0c..b08f2023748c
> >> 100644
> >> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> >> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> >> @@ -8,7 +8,7 @@
> >>
> >> #if defined(CONFIG_MACH_SUN9I)
> >> #include
> >>
> >> -#elif defined(CONFIG_MACH_SUN50I_H6)
> >> +#elif defined(CONFIG_SUN50I_GEN_H6)
> >>
> >> #include
> >> #else
> >> #include
> >>
> >> diff --git a/arch/arm/include/asm/arch-sunxi/timer.h
> >> b/arch/arm/include/asm/arch-sunxi/timer.h index
> >> 6f138d04b806..bb5626d893bb 100644
> >> --- a/arch/arm/include/asm/arch-sunxi/timer.h
> >> +++ b/arch/arm/include/asm/arch-sunxi/timer.h
> >> @@ -76,7 +76,7 @@ struct sunxi_timer_reg {
> >>
> >>struct sunxi_tgp tgp[4];
> >>u8 res5[8];
> >>u32 cpu_cfg;
> >>
> >> -#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
> >> +#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
> >>
> >>u8 res3[16];
> >>struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
> >>
> >> #endif
> >>
> >> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> >> index 49ef217f08c0..1cf79bad7cf6 100644
> >> --- a/arch/arm/mach-sunxi/Kconfig
> >> +++ b/arch/arm/mach-sunxi/Kconfig
> >> @@ -82,7 +82,7 @@ config SUN8I_RSB
> >>
> >> config SUNXI_SRAM_ADDRESS
> >>
> >>hex
> >>default 0x1 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
> >>
> >> - default 0x2 if MACH_SUN50I_H6
> >> + default 0x2 if SUN50I_GEN_H6
> >>
> >>default 0x0
> >>---help---
> >>Older Allwinner SoCs have their mask boot ROM mapped just below
4GB,
> >>
> >> @@ -108,6 +108,15 @@ config SUNXI_GEN_SUN6I
> >>
> >>separate ahb reset control registers, custom pmic bus, new style
> >>watchdog, etc.
> >>
> >> +config SUN50I_GEN_H6
> >
> > The new memory map is also used for 32-bit SoCs V5 (sun8iw12p1) and
> > newer. So this is not sun50i-specific, and I'd suggest SUNXI_GEN_H6 (or
> > even SUNXI_GEN_H6_V5). It is unfortunate there appears to be no name for
> > this family.
>
> Yeah, the Allwinner generation naming being *core* dependent is really
> annyoing and not helpful.
> I am fine with a rename, but then it would be very close to
> "CONFIG_SUNXI_GEN_SUN6I", which is quite confusing to any readers
> (already stumbled upon it myself in patch 04/17).
Re: [linux-sunxi] LRADC on A20
Hello Gediz, thank you for your kind reply. in attachment the files describing the device tree. lradc is noted in the .dtsi and is disabled for default: to enable it I'm using the overlay lradc_enable.dtbo (the source is lradc-enable.dts) the dmesg and lsmod outputs are in the related .txt Thank you again for your time. Best regards, Paolo Cremonese . Il giorno lun 4 gen 2021 alle ore 08:44 Nazım Gediz AYDINDOĞMUŞ < gediz.aydindog...@genemek.com> ha scritto: > On 1.01.2021 13:52, Paolo Cremonese wrote: > > Hi All, > > I need to use ADC0 of A20 using kernel 5.8 > > With old kernels (3.4) I had to add sun4i-keyboard module. > > In new kernels, I have seen that the device tree has a node called lradc > > which should load the driver sun4i-lradc-keys > > > > The driver is built, but it is not in the modules.builtin file. > > Enabling the lradc node in the device tree the module is not loaded. > > loading it using insmod the driver seems inactive. > > > > What I'm doing of wrong ? > > > > Thanks in advance, > > Paolo Cremonese > > Hello Paolo, > > Can you please send the content of your DTS file, and output of dmesg > and lsmod, if you are still working on it. I can give it a try for you. > > Regards, > Gediz > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAO20hp-mxUnmjQAp%2BLTxKD9Q05bh%3D%2BJ9N6r3APTd3q-k7jgbCw%40mail.gmail.com. [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 5.8.18-olimex (root@runner-cpbkaozn-project-1-concurrent-0) (arm-linux-gnueabihf-gcc (Debian 8.3.0-2) 8.3.0, GNU ld (GNU Binutils for Debian) 2.31.1) #140443 SMP Thu Nov 5 14:05:55 UTC 2020 [0.00] CPU: ARMv7 Processor [410fc074] revision 4 (ARMv7), cr=50c5387d [0.00] CPU: div instructions available: patching division code [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] OF: fdt: Machine model: Olimex A20-OLinuXino-LIME [0.00] Memory policy: Data cache writealloc [0.00] Reserved memory: created CMA memory pool at 0x4a00, size 96 MiB [0.00] OF: reserved mem: initialized node default-pool, compatible id shared-dma-pool [0.00] Zone ranges: [0.00] Normal [mem 0x4000-0x5fff] [0.00] HighMem empty [0.00] Movable zone start for each node [0.00] Early memory node ranges [0.00] node 0: [mem 0x4000-0x5fff] [0.00] Initmem setup node 0 [mem 0x4000-0x5fff] [0.00] On node 0 totalpages: 131072 [0.00] Normal zone: 1152 pages used for memmap [0.00] Normal zone: 0 pages reserved [0.00] Normal zone: 131072 pages, LIFO batch:31 [0.00] psci: probing for conduit method from DT. [0.00] psci: Using PSCI v0.1 Function IDs from DT [0.00] percpu: Embedded 20 pages/cpu s50060 r8192 d23668 u81920 [0.00] pcpu-alloc: s50060 r8192 d23668 u81920 alloc=20*4096 [0.00] pcpu-alloc: [0] 0 [0] 1 [0.00] Built 1 zonelists, mobility grouping on. Total pages: 129920 [0.00] Kernel command line: root=PARTUUID=e01b729c-01 rootwait console=ttyS0,115200 panic=10 loglevel=4 [0.00] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear) [0.00] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear) [0.00] allocated 524288 bytes of page_ext [0.00] mem auto-init: stack:off, heap alloc:off, heap free:off [0.00] Memory: 395792K/524288K available (10240K kernel code, 1260K rwdata, 3148K rodata, 1024K init, 328K bss, 30192K reserved, 98304K cma-reserved, 0K highmem) [0.00] random: get_random_u32 called from __kmem_cache_create+0x2b/0x3ac with crng_init=0 [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [0.00] ftrace: allocating 43513 entries in 85 pages [0.00] ftrace: allocated 85 pages with 4 groups [0.00] rcu: Hierarchical RCU implementation. [0.00] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2. [0.00] Rude variant of Tasks RCU enabled. [0.00] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [0.00] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 [0.00] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 [0.00] GIC: Using split EOI/Deactivate mode [0.00] arch_timer: cp15 timer(s) running at 24.00MHz (phys). [0.00] clocksource: arch_sys_counter: mask: 0xff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns [0.07] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns [
[linux-sunxi] Re: [PATCH net 2/4] net: stmmac: dwmac-sun8i: Balance internal PHY resource references
On Sun, Jan 3, 2021 at 7:17 PM Samuel Holland wrote:
>
> While stmmac_pltfr_remove calls sun8i_dwmac_exit, the sun8i_dwmac_init
> and sun8i_dwmac_exit functions are also called by the stmmac_platform
> suspend/resume callbacks. They may be called many times during the
> device's lifetime and should not release resources used by the driver.
>
> Furthermore, there was no error handling in case registering the MDIO
> mux failed during probe, and the EPHY clock was never released at all.
>
> Fix all of these issues by moving the deinitialization code to a driver
> removal callback. Also ensure the EPHY is powered down before removal.
>
> Fixes: 634db83b8265 ("net: stmmac: dwmac-sun8i: Handle integrated/external
> MDIOs")
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to linux-sunxi+unsubscr...@googlegroups.com.
To view this discussion on the web, visit
https://groups.google.com/d/msgid/linux-sunxi/CAGb2v66j%2Bxj-Pq5ijcb%2BHwLUf0TZkDDnpHcTjj20Q%2BM2UEtqUQ%40mail.gmail.com.
[linux-sunxi] Re: [PATCH net 1/4] net: stmmac: dwmac-sun8i: Fix probe error handling
On Sun, Jan 3, 2021 at 7:17 PM Samuel Holland wrote:
>
> stmmac_pltfr_remove does three things in one function, making it
> inapproprate for unwinding the steps in the probe function. Currently,
> a failure before the call to stmmac_dvr_probe would leak OF node
> references due to missing a call to stmmac_remove_config_dt. And an
> error in stmmac_dvr_probe would cause the driver to attempt to remove a
> netdevice that was never added. Fix these by reordering the init and
> splitting out the error handling steps.
>
> Fixes: 9f93ac8d4085 ("net-next: stmmac: Add dwmac-sun8i")
> Fixes: 40a1dcee2d18 ("net: ethernet: dwmac-sun8i: Use the correct function in
> exit path")
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to linux-sunxi+unsubscr...@googlegroups.com.
To view this discussion on the web, visit
https://groups.google.com/d/msgid/linux-sunxi/CAGb2v67c-2ZHadh%3DEs6eKyRYOHWi%2BQ5Tf9dxX_dkbK-Z%3DmHs-g%40mail.gmail.com.
[linux-sunxi] Re: [PATCH v2 4/4] arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection
On 03/01/2021 10:00, Samuel Holland wrote:
> On boards where the only peripheral connected to PL0/PL1 is an X-Powers
> PMIC, configure the connection to use the RSB bus rather than the I2C
> bus. Compared to the I2C controller that shares the pins, the RSB
> controller allows a higher bus frequency, and it is more CPU-efficient.
But is it really necessary to change the DTs for those boards in this
way? It means those newer DTs now become incompatible with older
kernels, and I don't know if those reasons above really justify this.
I understand that we officially don't care about "newer DTs on older
kernels", but do we really need to break this deliberately, for no
pressing reasons?
Cheers,
Andre
P.S. I am fine with supporting RSB on H6, and even using it on new DTs,
just want to avoid breaking existing ones.
> Signed-off-by: Samuel Holland
> ---
> .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 38 +--
> .../dts/allwinner/sun50i-h6-orangepi-3.dts| 14 +++
> .../dts/allwinner/sun50i-h6-orangepi.dtsi | 22 +--
> 3 files changed, 37 insertions(+), 37 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> index 7c9dbde645b5..3452add30cc4 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> @@ -150,12 +150,28 @@ {
> vcc-pg-supply = <_aldo1>;
> };
>
> -_i2c {
> +_ir {
> + linux,rc-map-name = "rc-beelink-gs1";
> + status = "okay";
> +};
> +
> +_pio {
> + /*
> + * FIXME: We can't add that supply for now since it would
> + * create a circular dependency between pinctrl, the regulator
> + * and the RSB Bus.
> + *
> + * vcc-pl-supply = <_aldo1>;
> + */
> + vcc-pm-supply = <_aldo1>;
> +};
> +
> +_rsb {
> status = "okay";
>
> - axp805: pmic@36 {
> + axp805: pmic@745 {
> compatible = "x-powers,axp805", "x-powers,axp806";
> - reg = <0x36>;
> + reg = <0x745>;
> interrupt-parent = <_intc>;
> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> interrupt-controller;
> @@ -273,22 +289,6 @@ sw {
> };
> };
>
> -_ir {
> - linux,rc-map-name = "rc-beelink-gs1";
> - status = "okay";
> -};
> -
> -_pio {
> - /*
> - * PL0 and PL1 are used for PMIC I2C
> - * don't enable the pl-supply else
> - * it will fail at boot
> - *
> - * vcc-pl-supply = <_aldo1>;
> - */
> - vcc-pm-supply = <_aldo1>;
> -};
> -
> {
> clocks = <_osc32k>;
> };
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
> index 15c9dd8c4479..16702293ac0b 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
> @@ -175,12 +175,16 @@ {
> vcc-pg-supply = <_vcc_wifi_io>;
> };
>
> -_i2c {
> +_ir {
> + status = "okay";
> +};
> +
> +_rsb {
> status = "okay";
>
> - axp805: pmic@36 {
> + axp805: pmic@745 {
> compatible = "x-powers,axp805", "x-powers,axp806";
> - reg = <0x36>;
> + reg = <0x745>;
> interrupt-parent = <_intc>;
> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> interrupt-controller;
> @@ -291,10 +295,6 @@ sw {
> };
> };
>
> -_ir {
> - status = "okay";
> -};
> -
> {
> clocks = <_osc32k>;
> };
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> index ebc120a9232f..23e3cb2ffd8d 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> @@ -112,12 +112,20 @@ {
> vcc-pg-supply = <_aldo1>;
> };
>
> -_i2c {
> +_ir {
> + status = "okay";
> +};
> +
> +_pio {
> + vcc-pm-supply = <_bldo3>;
> +};
> +
> +_rsb {
> status = "okay";
>
> - axp805: pmic@36 {
> + axp805: pmic@745 {
> compatible = "x-powers,axp805", "x-powers,axp806";
> - reg = <0x36>;
> + reg = <0x745>;
> interrupt-parent = <_intc>;
> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> interrupt-controller;
> @@ -232,14 +240,6 @@ sw {
> };
> };
>
> -_ir {
> - status = "okay";
> -};
> -
> -_pio {
> - vcc-pm-supply = <_bldo3>;
> -};
> -
> {
> clocks = <_osc32k>;
> };
>
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to linux-sunxi+unsubscr...@googlegroups.com.
To view this discussion on the web, visit
https://groups.google.com/d/msgid/linux-sunxi/a6c2eac4-7e98-ecb4-ee8a-d67a7f1b6871%40arm.com.
Re: [linux-sunxi] [PATCH 02/17] sunxi: Introduce common symbol for H6 like SoCs
On 03/01/2021 23:43, Samuel Holland wrote:
Hi Jernej,
thanks for that patch, that's a nice solution to avoid those long #ifdef
chains!
> On 1/3/21 3:26 AM, Jernej Skrabec wrote:
>> It turns out that there are at least 2 other SoCs which have basically
>> the same memory map, similar clocks and other features as H6. It's very
>> likely that we'll see more such SoCs in the future. In order to ease
>> porting to new SoCs and lower ifdef clutter, introduce common symbol for
>> them.
>>
>> Signed-off-by: Jernej Skrabec
>> ---
>> arch/arm/include/asm/arch-sunxi/boot0.h | 2 +-
>> arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
>> arch/arm/include/asm/arch-sunxi/cpu.h | 2 +-
>> arch/arm/include/asm/arch-sunxi/timer.h | 2 +-
>> arch/arm/mach-sunxi/Kconfig | 21 +
>> arch/arm/mach-sunxi/Makefile| 2 +-
>> arch/arm/mach-sunxi/board.c | 4 ++--
>> arch/arm/mach-sunxi/rmr_switch.S| 2 +-
>> common/spl/Kconfig | 4 ++--
>> include/configs/sun50i.h| 2 +-
>> 10 files changed, 24 insertions(+), 19 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h
>> b/arch/arm/include/asm/arch-sunxi/boot0.h
>> index 46d0f0666c2b..e8e8e38f0556 100644
>> --- a/arch/arm/include/asm/arch-sunxi/boot0.h
>> +++ b/arch/arm/include/asm/arch-sunxi/boot0.h
>> @@ -39,7 +39,7 @@
>> .word 0xf57ff06f // isb sy
>> .word 0xe320f003 // wfi
>> .word 0xeafd // b @wfi
>> -#ifndef CONFIG_MACH_SUN50I_H6
>> +#ifndef CONFIG_SUN50I_GEN_H6
>> .word 0x017000a0 // writeable RVBAR mapping address
>> #else
>> .word 0x09010040 // writeable RVBAR mapping address
>> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
>> b/arch/arm/include/asm/arch-sunxi/clock.h
>> index 5994130e6b54..cbbe5c7a1e68 100644
>> --- a/arch/arm/include/asm/arch-sunxi/clock.h
>> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
>> @@ -16,7 +16,7 @@
>> /* clock control module regs definition */
>> #if defined(CONFIG_MACH_SUN8I_A83T)
>> #include
>> -#elif defined(CONFIG_MACH_SUN50I_H6)
>> +#elif defined(CONFIG_SUN50I_GEN_H6)
>> #include
>> #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
>>defined(CONFIG_MACH_SUN50I)
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
>> b/arch/arm/include/asm/arch-sunxi/cpu.h
>> index 8b57d24e2f0c..b08f2023748c 100644
>> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
>> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
>> @@ -8,7 +8,7 @@
>>
>> #if defined(CONFIG_MACH_SUN9I)
>> #include
>> -#elif defined(CONFIG_MACH_SUN50I_H6)
>> +#elif defined(CONFIG_SUN50I_GEN_H6)
>> #include
>> #else
>> #include
>> diff --git a/arch/arm/include/asm/arch-sunxi/timer.h
>> b/arch/arm/include/asm/arch-sunxi/timer.h
>> index 6f138d04b806..bb5626d893bb 100644
>> --- a/arch/arm/include/asm/arch-sunxi/timer.h
>> +++ b/arch/arm/include/asm/arch-sunxi/timer.h
>> @@ -76,7 +76,7 @@ struct sunxi_timer_reg {
>> struct sunxi_tgp tgp[4];
>> u8 res5[8];
>> u32 cpu_cfg;
>> -#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
>> +#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
>> u8 res3[16];
>> struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
>> #endif
>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
>> index 49ef217f08c0..1cf79bad7cf6 100644
>> --- a/arch/arm/mach-sunxi/Kconfig
>> +++ b/arch/arm/mach-sunxi/Kconfig
>> @@ -82,7 +82,7 @@ config SUN8I_RSB
>> config SUNXI_SRAM_ADDRESS
>> hex
>> default 0x1 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
>> -default 0x2 if MACH_SUN50I_H6
>> +default 0x2 if SUN50I_GEN_H6
>> default 0x0
>> ---help---
>> Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
>> @@ -108,6 +108,15 @@ config SUNXI_GEN_SUN6I
>> separate ahb reset control registers, custom pmic bus, new style
>> watchdog, etc.
>>
>> +config SUN50I_GEN_H6
>
> The new memory map is also used for 32-bit SoCs V5 (sun8iw12p1) and
> newer. So this is not sun50i-specific, and I'd suggest SUNXI_GEN_H6 (or
> even SUNXI_GEN_H6_V5). It is unfortunate there appears to be no name for
> this family.
Yeah, the Allwinner generation naming being *core* dependent is really
annyoing and not helpful.
I am fine with a rename, but then it would be very close to
"CONFIG_SUNXI_GEN_SUN6I", which is quite confusing to any readers
(already stumbled upon it myself in patch 04/17).
Any opinions?
>
>> +bool
>> +select FIT
>> +select SPL_LOAD_FIT
>> +select SUPPORT_SPL
>> +---help---
>> +Select this for sunxi SoCs which have H6 like peripherals, clocks
>> +and memory map.
>> +
>> config SUNXI_DRAM_DW
>> bool
>> ---help---
>> @@ -302,10 +311,7 @@ config MACH_SUN50I_H5
>> config MACH_SUN50I_H6
>> bool "sun50i (Allwinner H6)"
>> select ARM64
>> -
[linux-sunxi] Re: [PATCH 0/4] bus: sunxi-rsb: Implement power managment
Hi, On Sun, Jan 3, 2021 at 7:06 PM Samuel Holland wrote: > > This series adds system (complete power down) and runtime (clock gate) > PM hooks to the RSB controller driver. Tested on A64 and H6. > > Samuel Holland (4): > bus: sunxi-rsb: Move OF match table > bus: sunxi-rsb: Split out controller init/exit functions > bus: sunxi-rsb: Implement suspend/resume/shutdown callbacks > bus: sunxi-rsb: Implement runtime power management > > drivers/bus/sunxi-rsb.c | 211 > 1 file changed, 150 insertions(+), 61 deletions(-) Looks good to me. Acked-by: Chen-Yu Tsai I already queued them up locally, but I think it's best to give other people some time to review as well. ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAGb2v6704ybnn2mOs_hGZm_ZM2bRAztDNZNx8CyASMJ8Z4GdCA%40mail.gmail.com.
Re: [linux-sunxi] [PATCH v2 0/4] Allwinner H6 RSB support
Hi,
On Sun, Jan 03, 2021 at 04:00:03AM -0600, Samuel Holland wrote:
> The Allwinner H6 SoC contains an RSB controller. It is almost completely
> undocumented, so it was missed when doing the initial SoC bringup.
>
> This series adds the clock/reset, pin configuration, and device tree
> node needed to use the RSB controller. Since RSB is faster, simpler, and
> generally more reliable than the I2C controller IP in the SoC, switch to
> using it where possible.
>
> This was tested on an Orange Pi 3 and a Pine H64 model B. This series
> does not switch the Pine H64 to use RSB, as doing so would prevent
> accessing the external RTC that shares the I2C bus.
>
> Changes v1->v2:
> - Put the new values at the end of the DT binding headers
>
> Samuel Holland (4):
> clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset
> pinctrl: sunxi: h6-r: Add s_rsb pin functions
> arm64: dts: allwinner: h6: Add RSB controller node
> arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection
I queued up patches 1, 3, and 4 locally for v5.12. Obviously this won't
work unless the pinctrl patch is also queued up, so they won't be pushed
out until that happens.
Regarding patch 3, I replaced the clock and reset macros with raw
numbers to get rid of cross-tree dependencies. The following fix
will be posted for v5.12 later on during its RC cycle.
>8
commit 0b4781666adc5e19c4d4fb4a2bff33883181cc39
Author: Chen-Yu Tsai
Date: Mon Jan 4 16:19:17 2021 +0800
arm64: dts: allwinner: h6: Switch to macros for RSB clock/reset indices
The macros for the clock and reset indices for the RSB hardware block
were replaced with raw numbers when the RSB controller node was added.
This was done to avoid cross-tree dependencies.
Now that both the clk and DT changes have been merged, we can switch
back to using the macros.
Signed-off-by: Chen-Yu Tsai
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index d897697849d6..b043beea8e6e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -988,9 +988,9 @@ r_rsb: rsb@7083000 {
compatible = "allwinner,sun8i-a23-rsb";
reg = <0x07083000 0x400>;
interrupts = ;
- clocks = <_ccu 13>;
+ clocks = <_ccu CLK_R_APB2_RSB>;
clock-frequency = <300>;
- resets = <_ccu 7>;
+ resets = <_ccu RST_R_APB2_RSB>;
pinctrl-names = "default";
pinctrl-0 = <_rsb_pins>;
status = "disabled";
>8
>
> .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 38 +--
> .../dts/allwinner/sun50i-h6-orangepi-3.dts| 14 +++
> .../dts/allwinner/sun50i-h6-orangepi.dtsi | 22 +--
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 ++
> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c| 5 +++
> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h| 2 +-
> drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 2 +
> include/dt-bindings/clock/sun50i-h6-r-ccu.h | 2 +
> include/dt-bindings/reset/sun50i-h6-r-ccu.h | 1 +
> 9 files changed, 67 insertions(+), 38 deletions(-)
>
> --
> 2.26.2
>
> --
> You received this message because you are subscribed to the Google Groups
> "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to linux-sunxi+unsubscr...@googlegroups.com.
> To view this discussion on the web, visit
> https://groups.google.com/d/msgid/linux-sunxi/2021010317.32867-1-samuel%40sholland.org.
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to linux-sunxi+unsubscr...@googlegroups.com.
To view this discussion on the web, visit
https://groups.google.com/d/msgid/linux-sunxi/X/LSdICpXl6vT65y%40wens.csie.org.
