No worries, thanks for the reply.
Phil
On Tue, Jan 28, 2014 at 3:57 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 01/27/2014 10:28 PM, Phil Scull wrote:
Hans,
I still have trouble getting the HDMI monitor to come out of suspend
running linaro on CT.
Removing the lines that
Hello Rob,
On 23/01/2014 16:22, Rob Herring wrote:
On Sat, Jan 11, 2014 at 7:38 AM, boris brezillon
b.brezil...@overkiz.com wrote:
On 08/01/2014 15:21, Boris BREZILLON wrote:
Hello,
This series add the sunxi NFC support with up to 8 NAND chip connected.
I'm still in the early stages drivers
Hello Brian,
On 23/01/2014 02:49, Brian Norris wrote:
+ Huang
Hi Boris,
On Wed, Jan 08, 2014 at 03:21:56PM +0100, Boris BREZILLON wrote:
The Hynix nand flashes store their ECC requirements in byte 4 of its id
(returned on READ ID command).
Signed-off-by: Boris BREZILLON
The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 46
The A31 has 4 SPI controllers. Add them in the DTSI.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sunxi.c | 45 +++
2
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/configs/sunxi_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 3e2259b..b5df4a5 100644
--- a/arch/arm/configs/sunxi_defconfig
+++
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/spi/spi-sun6i.txt |
On 28 January 2014 16:56, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 01/28/2014 02:29 PM, Michal Suchanek wrote:
Hello,
I have the sauce so I can presumably rip out the useful parts and make
own tool but here is what I get with pio:
root@A13:/sunxi-tools# ./pio print
usage: ./pio
Hello,
I found the problem.
I had different settings for debug uart and uart 0.
The ones for debug uart worked and when uart0 got initialized it broke.
Thanks
Michal
On 27 January 2014 14:48, Olliver Schinagl oliver+l...@schinagl.nl wrote:
On 27-01-14 13:38, jonsm...@gmail.com wrote:
Are
On Wed, Jan 29, 2014 at 12:10:48PM +0100, Maxime Ripard wrote:
+config SPI_SUN6I
+ tristate Allwinner A31 SPI controller
+ depends on ARCH_SUNXI || COMPILE_TEST
+ select PM_RUNTIME
+ help
+ This enables using the SPI controller on the Allwinner A31 SoCs.
+
A select
On Tue, Jan 28, 2014 at 10:02:46PM +0100, Carlo Caione wrote:
Hi,
On Tue, Jan 28, 2014 at 5:41 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Tue, Jan 28, 2014 at 12:02:23PM +0100, Hans de Goede wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi,
On
On Wed, Jan 29, 2014 at 1:58 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
So, to sum things up, what you see is something like:
handle_level_irq
| devicedevice
| mask ack handler irq acked unmask
| |
On Wed, Jan 29, 2014 at 12:25:20PM +, Mark Brown wrote:
On Wed, Jan 29, 2014 at 12:10:48PM +0100, Maxime Ripard wrote:
+config SPI_SUN6I
+ tristate Allwinner A31 SPI controller
+ depends on ARCH_SUNXI || COMPILE_TEST
+ select PM_RUNTIME
+ help
+ This enables using
On Wed, Jan 29, 2014 at 1:28 AM, Luc Verhaegen l...@skynet.be wrote:
On Tue, Jan 28, 2014 at 04:16:00PM -0500, jonsm...@gmail.com wrote:
I know that our support for A31 is severely lacking, but please work
through the http://linux-sunxi.org/New_Device_howto anyway.
Not sure I am going to
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
Documentation/devicetree/bindings/mtd/nand.txt |3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt
Add a function to retrieve NAND timing mode (ONFI timing mode) from a given
DT node.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/of/of_mtd.c| 19 +++
include/linux/of_mtd.h |8
2 files changed, 27 insertions(+)
diff --git
Hello,
This series adds support for the sunxi NAND Flash Controller (NFC).
This controller supports up to 8 NAND chip connected.
I'm still in the early stages drivers development and some key features are
missing, but it's usable (I tested it on the cubietruck board).
Here's what's missing:
-
Add a converter to retrieve NAND timings from an ONFI NAND timing mode.
This only support SDR NAND timings for now.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/mtd/nand/Makefile |2 +-
drivers/mtd/nand/nand_timings.c | 248
Some chip do not support automatic retrieval of ECC level requirements.
Provide an helper function to retrieve these requirements from DT.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/of/of_mtd.c| 25 +
include/linux/of_mtd.h |7 +++
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
.../devicetree/bindings/mtd/sunxi-nand.txt | 46
1 file changed, 46 insertions(+)
create mode 100644
Define the NAND pinctrl configs.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
arch/arm/boot/dts/sun7i-a20.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 031de97..5828923 100644
---
On 13 January 2014 10:02, boris brezillon b.brezil...@overkiz.com wrote:
Hi Henrik,
On 11/01/2014 22:11, Henrik Nordström wrote:
bbrezillon thanks for pointing out your documents
bbrezillon I'm trying to get the NAND driver with HW ECC (and HW RND)
without using DMA at all
I tried many
On 29 January 2014 16:43, boris brezillon dev b.brezillon@gmail.com wrote:
Hello Michal,
On 29/01/2014 16:11, Michal Suchanek wrote:
On 13 January 2014 10:02, boris brezillon b.brezil...@overkiz.com wrote:
boot 0 part properties:
- uses sequential ECC
- uses 1024 bytes ECC blocks
-
On 29/01/2014 17:08, Michal Suchanek wrote:
On 29 January 2014 16:43, boris brezillon dev b.brezillon@gmail.com wrote:
Hello Michal,
On 29/01/2014 16:11, Michal Suchanek wrote:
On 13 January 2014 10:02, boris brezillon b.brezil...@overkiz.com wrote:
boot 0 part properties:
- uses
From 7c7364e458ea7bca6756cc2d1cd3e1e8c57a9c96 Mon Sep 17 00:00:00 2001
In-Reply-To:
a1920c011a6968f4b3b0f2ccfdf98289be301c5e.1391014497.git.hramr...@gmail.com
Signed-off-by: Michal Suchanek hramr...@gmail.com
---
sys_config/a13/inet_86vs.fex | 14 ++
1 file changed, 14
From a1920c011a6968f4b3b0f2ccfdf98289be301c5e Mon Sep 17 00:00:00 2001
Signed-off-by: Michal Suchanek hramr...@gmail.com
---
sys_config/a13/inet_86vs.fex | 735 ++
1 file changed, 735 insertions(+)
create mode 100644 sys_config/a13/inet_86vs.fex
diff
From 1bb92f91a32c9ed698b0e5cc4aaa48e60d4b46da Mon Sep 17 00:00:00 2001
In-Reply-To:
a1920c011a6968f4b3b0f2ccfdf98289be301c5e.1391014497.git.hramr...@gmail.com
Signed-off-by: Michal Suchanek hramr...@gmail.com
---
sys_config/a13/inet_86vs.fex |8 +++-
1 file changed, 3 insertions(+), 5
Looks good. Applied.
tis 2014-01-28 klockan 22:06 +0100 skrev Michal Suchanek:
From c1c9a0432331a59e047a3330f89e2cca27e77b25 Mon Sep 17 00:00:00 2001
Signed-off-by: Michal Suchanek hramr...@gmail.com
---
pio.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
On Wed, Jan 29, 2014 at 03:34:18PM +0100, Boris BREZILLON wrote:
+static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
+ struct device_node *np)
+{
+ const struct nand_sdr_timings *timings;
+ u32 min_clk_period = 0;
+ int ret;
Hello Rob,
Le 29/01/2014 18:11, Rob Herring a écrit :
On Wed, Jan 29, 2014 at 8:34 AM, Boris BREZILLON
b.brezillon@gmail.com wrote:
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
Le 29/01/2014 19:02, Gupta, Pekon a écrit :
Dear Rob, and other DT maintainers,
From: Rob Herring
[...]
+- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
+ standard.
Add to generic nand binding.
+- allwinner,rb : shall contain the native Ready/Busy ids.
+ or
+-
Le 29/01/2014 19:02, Gupta, Pekon a écrit :
Dear Rob, and other DT maintainers,
From: Rob Herring
[...]
+- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
+ standard.
Add to generic nand binding.
+- allwinner,rb : shall contain the native Ready/Busy ids.
+ or
+-
Dear Rob, and other DT maintainers,
From: Rob Herring
[...]
+- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
+ standard.
Add to generic nand binding.
+- allwinner,rb : shall contain the native Ready/Busy ids.
+ or
+- rb-gpios : shall contain the gpios used as R/B
Dear Rob, and other DT maintainers,
(apologies, fixed typos in earlier mail)
From: Rob Herring
[...]
+- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
+ standard.
Add to generic nand binding.
+- allwinner,rb : shall contain the native Ready/Busy ids.
+ or
+-
On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
Documentation/devicetree/bindings/mtd/nand.txt |3 +++
1 file changed, 3 insertions(+)
On Wed, Jan 29, 2014 at 10:56:42AM -0700, Jason Gunthorpe wrote:
On Wed, Jan 29, 2014 at 03:34:18PM +0100, Boris BREZILLON wrote:
[..]
+static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
[..]
+ ret = sunxi_nand_chip_init_timings(chip, np);
+ if
On Wed, Jan 29, 2014 at 03:46:20PM -0300, Ezequiel Garcia wrote:
After CE# has been pulled high and then transitioned low again, the host
should issue a Set Features to select the appropriate asynchronous timing
mode.
Oh, I had forgot you should do a set feature too
Boris, I think the
On 2014-01-24, neje...@gmail.com neje...@gmail.com wrote:
Dear All: So far my A13 chinese tablet works fine. Any idea how to rotate the
Screen 90 degrees to have it on Portrait as default? XRANDR does not work,
fbcon works on console mode ( echoing 1 to ../rotate_all), I am using lightdm
+
From d8d50b936a98f94f5a216bb99d6b519530778193 Mon Sep 17 00:00:00 2001
Signed-off-by: Michal Suchanek hramr...@gmail.com
---
board/sunxi/Makefile|1 +
board/sunxi/dram_inet86vs.c | 29 +
boards.cfg |2 ++
3 files changed, 32
Im Trying to use Uart 6 and Uart7 on PI Ports
I see a valid ttl signal on the Input pin of the Uarts Read Pin but I can not
read anything in linux
On uart7 I can send out data
On uart 6 I can neither send nor receive data (measured the ttl signals with
scope, no data showing up on writ, valid
Hi Maxime,
El 29/01/14 08:10, Maxime Ripard escribió:
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
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