This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by: Carlo Caione
Acked-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 8
arch/arm/boot/dts/sun7i-a20.dtsi | 8
2 files changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.
Signed-off-by: Carlo Caione
Acked-by: Maxime Ripard
---
drivers/irqchip/Makefile| 1 +
drivers
Added documentation for NMI irqchip.
Signed-off-by: Carlo Caione
Acked-by: Maxime Ripard
---
.../allwinner,sun67i-sc-nmi.txt| 27 ++
1 file changed, 27 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun
Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI.
Three register are present to (un)mask, control and acknowledge NMI.
These two patches add a new irqchip driver in cascade with GIC.
Changes since v1:
- added binding document
Changes since v2:
- fixed tr
On Wed, Mar 26, 2014 at 03:38:05PM +0100, Hans de Goede wrote:
> Hi,
Hi Hans,
> On 03/26/2014 11:04 AM, Hans de Goede wrote:
> > Hi,
> >
> > On 03/26/2014 10:39 AM, Maxime Ripard wrote:
> >> On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote:
> >>> Hi,
> >>>
> >>> On 03/19/2014 08:21 P
This is necessary to support the sun6i-a31.
Signed-off-by: Hans de Goede
---
drivers/mmc/host/sunxi-mmc.c | 19 +++
drivers/mmc/host/sunxi-mmc.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index a16abd2..6b86
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index cd0d4b0..45b5775 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/ar
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 59
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 45b5775..8fa124b 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
Hi All,
Here is a patch-series adding mmc support to sun6i. This actually turned
out to be quite easy :)
Note this is RFC only as the entire sunxi mmc code is not upstream yet, as
such this patch sets sits on top of the sunxi-devel branch. You can also find
it in my tree:
https://github.com/jwrde
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31-m9.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts
b/arch/arm/boot/dts/sun6i-a31-m9.dts
index c95ee77..22837bc 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm
Add a new sun6i-a31-m9 dts file for the Mele M9 / Mele A1000G Quad. These
HTPCs use the same board in a different case, for more details see:
http://linux-sunxi.org/Mele_M9
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun6i-a31-m9.dts | 30 +++
On 03/26/2014 04:47 PM, Hans de Goede wrote:
Hi,
On 03/26/2014 04:37 PM, Olliver Schinagl wrote:
P.S. one small issue is that the _config name has to match whatever is in
boards.cfg (obvious) including capitalization. I think we had a patch that
fixed this a while ago, so I will track this do
On Tue, 25 Mar 2014 03:23:54 +0530
Rajesh Mallah wrote:
> I also observed that a clone of the rootfs from Mele M3 to another
> A20 based TB Box consistently performed slower than Mele M3.
>
> MeleM3 :18.95 secs
> Other A20: 25 secs
>
> the dump from a10-meminfo-static were same in bot
I tried to start cleaning up the u-boot DRAM setup code for sunxi and
found a bug(?) that *could* be responsible for the low possible memory
frequencies on some boards like cubietruck.
The patches don't raise any memory frequencies, but they could make it
possible to raise them. My cubietruck runs
This patch unifies sun4i and sun[5,7]i autorefresh setup functions
and adds proper tRFC calculation.
tRFC (REF command to ACT time) depends on DDR type and chip density.
On sun4i there were two steps, 127.5ns for <=1Gb density and 327.5ns
for the rest. This fits DDR2 specification for 1Gb and 4Gb
Cubietruck has four 4Gb x8 DDR3 chips, not two 8Gb x16. This doesn't
change anything for users, but reports correct values for timing
parameters depending on density.
Signed-off-by: Jens Kuske
---
board/sunxi/dram_cubietruck.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Marcus Cooper
Signed-off-by: Marcus Cooper
---
sys_config/a20/mk808c.fex | 1013 +
1 file changed, 1013 insertions(+)
create mode 100644 sys_config/a20/mk808c.fex
diff --git a/sys_config/a20/mk808c.fex b/sys_config/a20/mk808c.fex
new file mode
Hi,
On 03/26/2014 04:37 PM, Olliver Schinagl wrote:
> P.S. one small issue is that the _config name has to match whatever is in
> boards.cfg (obvious) including capitalization. I think we had a patch that
> fixed this a while ago, so I will track this down and see if i can find it
> again.
Thi
On Wed, Mar 26, 2014 at 04:47:47PM +0100, Hans de Goede wrote:
> Hi,
>
> On 03/26/2014 04:37 PM, Olliver Schinagl wrote:
> > P.S. one small issue is that the _config name has to match whatever is in
> > boards.cfg (obvious) including capitalization. I think we had a patch that
> > fixed this a w
P.S. one small issue is that the _config name has to match whatever is
in boards.cfg (obvious) including capitalization. I think we had a patch
that fixed this a while ago, so I will track this down and see if i can
find it again.
Olliver
On 03/26/2014 04:36 PM, Olliver Schinagl wrote:
Hey a
Hey all,
Just letting you know, that a new upstream u-boot version has been
merged and pushed. If you are in dire need of some new u-boot version,
git pull, compile and flash!
Though I don't recall there being a new feature ;)
It has been tested on the:
Olimexino-Lime
Cubieboard1
Cubieboard2
Dear Ian Campbell,
In message <1395826756.22808.13.ca...@kazak.uk.xensource.com> you wrote:
>
> > Please add a comment to explain that.
>
> Unless you object I think I'll do as Marek suggested name the function
> sunxi_name_to_gpio and make the #define to that, it seems more
> consistent that way
Hi,
On 03/26/2014 03:26 PM, Maxime Ripard wrote:
> On Wed, Mar 26, 2014 at 09:48:18AM -0400, Stefan Monnier wrote:
>>
>> Since my Mele A2000 keeps locking up when using the 3.4 kernel (as
>> reported here several months ago), I decided I should try the sunxi-next
>> kernel (my machine can be headl
Hi,
On 03/26/2014 11:04 AM, Hans de Goede wrote:
> Hi,
>
> On 03/26/2014 10:39 AM, Maxime Ripard wrote:
>> On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote:
>>> Hi,
>>>
>>> On 03/19/2014 08:21 PM, Carlo Caione wrote:
This patch adds DTS entries for NMI controller as child of GIC
On Wed, Mar 26, 2014 at 09:48:18AM -0400, Stefan Monnier wrote:
>
> Since my Mele A2000 keeps locking up when using the 3.4 kernel (as
> reported here several months ago), I decided I should try the sunxi-next
> kernel (my machine can be headless, it just needs USB and SATA support,
> basically).
maybe I'm wrong about needing to use Hans' u-boot. According to this thread
it's only required for A13, A20
https://groups.google.com/forum/#!msg/linux-sunxi/DC1QtgONxPM/MDfCtlv4fFIJ.
CK
On 26 March 2014 15:10, Code Kipper wrote:
> Hi Stefan,
> I also have the A2000 and did have problems with i
Hi Stefan,
I also have the A2000 and did have problems with it booting until MrNuke
fixed the MMC(the latest on sunxi-devel is 3.14.0.rc6). My setup is very
similar to yours(running Debian headless although without any external
devices). Looking at the size of the kernel then it seems that you will
SPI transfers were limited to one FIFO depth, which is 64 bytes.
This was an artificial limitation, however, as the hardware can handle
much larger bursts. To accommodate this, we enable the interrupt when
the Rx FIFO is 3/4 full, and drain the FIFO within the interrupt
handler. The 3/4 ratio was c
Since my Mele A2000 keeps locking up when using the 3.4 kernel (as
reported here several months ago), I decided I should try the sunxi-next
kernel (my machine can be headless, it just needs USB and SATA support,
basically).
So I got the sunxi-next branch from Github's linux-sunxi. Then did
m
Hi Boris,
I downloaded git repo from you link.
https://github.com/bbrezillon/linux-sunxi/
but what will the config file. so i can get uImage and modules to boot in
my A20 board.
so i can use sunxi_nand module to access my boot0 and boot1 partition.
i am using cubieboard2.
your help is greatl
On Wednesday, March 26, 2014 at 10:39:16 AM, Ian Campbell wrote:
> On Wed, 2014-03-26 at 10:03 +0100, Wolfgang Denk wrote:
> > Dear Ian Campbell,
> >
> > In message <1395822781.29683.12.ca...@dagon.hellion.org.uk> you wrote:
> > > On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
> > > > > +in
Hi,
On 03/26/2014 10:39 AM, Maxime Ripard wrote:
> On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 03/19/2014 08:21 PM, Carlo Caione wrote:
>>> This patch adds DTS entries for NMI controller as child of GIC.
>>>
>>> Signed-off-by: Carlo Caione
>>
>> Note this breaks
On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote:
> Hi,
>
> On 03/19/2014 08:21 PM, Carlo Caione wrote:
> > This patch adds DTS entries for NMI controller as child of GIC.
> >
> > Signed-off-by: Carlo Caione
>
> Note this breaks the kernel on sun6i / A31 since we don't have a
> pmi
On Wed, 2014-03-26 at 10:03 +0100, Wolfgang Denk wrote:
> Dear Ian Campbell,
>
> In message <1395822781.29683.12.ca...@dagon.hellion.org.uk> you wrote:
> > On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
> >
> > > > +int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
> > > > +int sunxi_gpio_get_c
Dear Ian Campbell,
In message <1395822781.29683.12.ca...@dagon.hellion.org.uk> you wrote:
> On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
>
> > > +int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
> > > +int sunxi_gpio_get_cfgpin(u32 pin);
> > > +int sunxi_gpio_set_drv(u32 pin, u32 val);
> > >
On Wednesday, March 26, 2014 at 09:33:01 AM, Ian Campbell wrote:
> On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
> > > +int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
> > > +int sunxi_gpio_get_cfgpin(u32 pin);
> > > +int sunxi_gpio_set_drv(u32 pin, u32 val);
> > > +int sunxi_gpio_set_pull(u32
Hi,
On Mon, Mar 24, 2014 at 04:05:35PM +0100, Hans de Goede wrote:
> I've taken a quick look at the mmc code we've for the A31 in the sunxi
> provided kernel sources and it seems 100% identical to the mmc controller
> in sun5i and sun7i. I've not yet gotten around to actually hooking things
> up i
On Wednesday, March 26, 2014 at 09:30:38 AM, Ian Campbell wrote:
> On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
> > > + cfg = readl(&pio->cfg[0] + index);
> > > + cfg &= ~(0xf << offset);
> > > + cfg |= val << offset;
> > > +
> > > + writel(cfg, &pio->cfg[0] + index);
> >
Hi,
On 03/24/2014 04:05 PM, Hans de Goede wrote:
> Hi,
>
> p.s.
>
> I've taken a quick look at the mmc code we've for the A31 in the sunxi
> provided kernel sources and it seems 100% identical to the mmc controller
> in sun5i and sun7i. I've not yet gotten around to actually hooking things
> up
Hi,
On 03/19/2014 08:21 PM, Carlo Caione wrote:
> This patch adds DTS entries for NMI controller as child of GIC.
>
> Signed-off-by: Carlo Caione
Note this breaks the kernel on sun6i / A31 since we don't have a
pmic driver there yet, and thus the nmi gets constantly fired without
anything clear
On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
> > +int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
> > +int sunxi_gpio_get_cfgpin(u32 pin);
> > +int sunxi_gpio_set_drv(u32 pin, u32 val);
> > +int sunxi_gpio_set_pull(u32 pin, u32 val);
> > +int name_to_gpio(const char *name);
> > +#define name
On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
> > + cfg = readl(&pio->cfg[0] + index);
> > + cfg &= ~(0xf << offset);
> > + cfg |= val << offset;
> > +
> > + writel(cfg, &pio->cfg[0] + index);
>
> clrsetbits_le32() here.
I looked at this transform in a few different contex
On Mon, 2014-03-24 at 21:52 +0100, Marek Vasut wrote:
> On Friday, March 21, 2014 at 10:54:18 PM, Ian Campbell wrote:
> > This has been stripped back for mainlining and supports only sun7i. These
> > changes are not useful by themselves but are split out to make the patch
> > sizes more manageable.
On Mon, 2014-03-24 at 23:42 +0100, Olliver Schinagl wrote:
[...]
> I've got a local cleanup patch set where I fixed this already to
> clrsetbits_le32
>[...]
> Same here, got that in my local tree too
Could you post what you've got please?
> >> +#ifdef CONFIG_SPL_BUILD
> >> +#define PLL1_CFG(N, K
Hi Emilio,
We want to connect matrix of small LCD displays to a A20 based system.
Due to the relatively big number of the displays and the relatively high
resolution
we need a lot of data to send to them in order to refresh them all.
SPI (we can go up to 20MHz ) is a slow interface for this app
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