Hi all:
I created a firmware extractor for these chips. Hope it is useful.
Some notes:
* Sometimes it fails in the first launch, but launching again with
exactly the same parameters works fine.
* Try to unload the touch module before running it, to avoid
interferences between both codes.
On 24 May 2015 at 14:37, Michal Suchanek hramr...@gmail.com wrote:
Hello,
I tried to update the kernel on my cubieboards to something recent and
while the a10 cubieboard works fine the a20 one won't boot.
Looking at the console I found that the culprit is mmc clock so I
disabled mmc clock
Hello,
I tried to update the kernel on my cubieboards to something recent and
while the a10 cubieboard works fine the a20 one won't boot.
Looking at the console I found that the culprit is mmc clock so I
disabled mmc clock gating and the board works.
I went as far back as 3.19 and the issue is
Forgot to comment that this code extracts the firmware from a running GSL168x
chip. This means that you should compile it statically and run it in the
original Android system, to get the firmware.
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linux-sunxi group.
The 250ms timeout is too short.
On my system enabling the oclk takes under 50ms and disabling slightly
over 100ms when idle. Under load disabling the clock can take over
350ms.
This does not make mmc clock gating look like good option to have on
sunxi but the system should not crash with mmc
The function sunxi_mmc_oclk_onoff filters out the SDXC_LOW_POWER_ON flag
but never sets it.
Set SDXC_LOW_POWER_ON when oclk is disabled.
Signed-off-by: Michal Suchanek hramr...@gmail.com
---
drivers/mmc/host/sunxi-mmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hello,
I had serious problems with root filesustem on SD card on Cubieboard2 when
clock gating was on.
It turns out that sunxi_mmc_oclk_onoff has way too short timeout ofr setting
the clock.
So here are some patches for
- bumping the timout
- spamming dmesg when the time to set the clock
On Wed, May 20, 2015 at 6:08 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Thu, May 14, 2015 at 02:10:11PM +0800, Chen-Yu Tsai wrote:
The A80 stores some magic flags in a portion of the secure SRAM. The
BROM jumps directly to the software entry point set by the SMP code
if the
Thank you very much! This tool is one that what is missed in complete set
of make it working GSL1680.
Have ported your code to baytrail.
1st - these lines I think is rudшmental in section include (it is
important for porting! ) and came from user space driver where was used
uinput device.
Hi Siarhei,
As the resident sunxi dram controller expert, what do you make of this:
[dram_para]
dram_baseaddr = 0x4000
dram_clk = 408
dram_type = 3
dram_rank_num = -1
dram_chip_density = -1
dram_io_width = -1
dram_bus_width = -1
dram_cas = 9
dram_zq = 0x7f
dram_odt_en = 0
dram_size = -1
Ok,
So fresh news and summary.
Many many thanks to Sergio Costas for his work and assistance. He wrote and
published FW extractor. I suppose it will be useful for someone trying to
make it works GSL1680.
In my case, Chuwi Vi8 super (baytrail architecture) it looks that chinese
developers put
Ok,
So fresh news and summary.
Many many thanks to Sergio Costas for his work and assistance. He wrote and
published FW extractor. I suppose it will be useful for someone trying to
make it works GSL1680.
In my case, Chuwi Vi8 super (baytrail architecture) it looks that chinese
developers put
Hi Michal,
On Mon, May 25, 2015 at 4:07 AM, Michal Suchanek hramr...@gmail.com wrote:
The 250ms timeout is too short.
On my system enabling the oclk takes under 50ms and disabling slightly
over 100ms when idle. Under load disabling the clock can take over
350ms.
This does not make mmc
Hi,
On Wed, May 20, 2015 at 11:55 PM, Chen-Yu Tsai w...@csie.org wrote:
Hi,
On Thu, May 21, 2015 at 2:38 PM, Lawrence Yu lawy...@gmail.com wrote:
Hi,
On Mon, May 18, 2015 at 11:03 PM, Lawrence Yu lawy...@gmail.com wrote:
Hi,
On Mon, May 18, 2015 at 8:01 PM, Chen-Yu Tsai
On Thu, May 21, 2015 at 09:47:35AM +0200, Maxime Ripard wrote:
On Mon, May 18, 2015 at 02:16:14PM +0530, Vinod Koul wrote:
+static enum dma_status sun4i_dma_tx_status(struct dma_chan *chan,
+dma_cookie_t cookie,
+
On Thursday, May 21, 2015 at 5:12:07 PM UTC+7, Luc Verhaegen wrote:
On Thu, May 21, 2015 at 03:00:14AM -0700, sand...@outlook.com wrote:
On Wednesday, January 22, 2014 at 10:52:27 PM UTC+7, Luc Verhaegen wrote:
On Wed, Jan 22, 2014 at 10:40:49AM -0500, ferar achkar wrote:
greetings Luc,
On Sun, May 24, 2015 at 10:04:16AM +0200, Corentin LABBE wrote:
For aes_cbc it exists a test with 3 SG with .tap = { 496 - 20, 4, 16 }
But my driver handle that. (multiple of 4)
What do you think about adding a test with 16 SG of 1 byte ? (or 3 + 2 + 3 +
8 * 1)
Sure please send a patch.
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