Hi,
On Wed, Aug 24, 2016 at 04:21:35PM +0800, Icenowy Zheng wrote:
> Hi Maxime,
>
> 24.08.2016, 14:02, "Maxime Ripard" :
> > Hi,
> >
> > On Tue, Aug 23, 2016 at 09:55:46PM +0800, Icenowy Zheng wrote:
> >> A23/A33 has a NAND controller which can now be used
Jens Kuske wrote:
> The H3 PLL5 used for DRAM barely manages to lock to the required
> frequency before DRAM controller starts, sometimes leading to wrong
> delay-line calibration results.
> This patch changes the PLL tuning parameters to the same values as
> boot0 used, which speeds up the