Hello!
>
> Since the driver is dm-driven this config not need.
I tried not to use this config but then driver don't get compiled.
You're talking about CONFIG_USB_EHCI and CONFIG_USB_EHCI_SUNXI, right ?
Thanks
Amit.
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On 24/10/16 09:20, Jagan Teki wrote:
> On Sun, Oct 23, 2016 at 3:22 AM, André Przywara
> wrote:
>> On 22/10/16 18:10, Jagan Teki wrote:
>>
>> Hi,
>>
>>> On Fri, Oct 21, 2016 at 6:54 AM, Andre Przywara
>>> wrote:
OHCI has a known limitation
On 21/10/16 11:28, Hans de Goede wrote:
> Hi,
>
> On 21-10-16 12:06, Andre Przywara wrote:
>> Hi,
>>
>> On 21/10/16 10:31, Jagan Teki wrote:
>>> On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara
>>> wrote:
The sun8i-emac driver works fine with the A64 Ethernet IP, but
Hi Stephen,
On Thu, Oct 20, 2016 at 11:46:01AM -0700, Stephen Boyd wrote:
> On 10/11, Maxime Ripard wrote:
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > new file mode 100644
> > index ..c0e96bf6d104
> > --- /dev/null
> > +++
On Mon, Oct 24, 2016 at 11:59:30AM +0800, Icenowy Zheng wrote:
> Allwinner SoC's PHY 0, when used as OTG controller, have no pmu part.
> The code that poke some unknown bit of PMU for H3/A64 didn't check
> the PHY, and will cause kernel oops when PHY 0 is used.
>
> Fixes: b3e0d141ca9f (phy:
Hi,
On Fri, Oct 21, 2016 at 10:08:06AM +0200, Jean-Francois Moine wrote:
> This patch adds a HDMI driver to the DE2 based Allwinner's SoCs
> as A83T and H3.
> Audio and video are supported.
>
> Signed-off-by: Jean-Francois Moine
Output from checkpatch:
total: 26 errors, 31
Hi Jonathan,
On Fri, Oct 21, 2016 at 11:30:01AM +1100, Jonathan Liu wrote:
> On 21 October 2016 at 05:00, Maxime Ripard
> wrote:
> > From: Andre Przywara
> >
> > Signed-off-by: Andre Przywara
> > Acked-by: Rob
Hi André,
On Mon, Oct 24, 2016 at 12:57:04AM +0100, André Przywara wrote:
> > + pio: pinctrl@1c20800 {
> > + compatible = "allwinner,sun50i-a64-pinctrl";
> > + reg = <0x01c20800 0x400>;
> > + interrupts = ,
> > +
On Sun, Oct 23, 2016 at 10:26:31AM +0200, LABBE Corentin wrote:
> On Thu, Oct 20, 2016 at 10:36:54PM +0200, Maxime Ripard wrote:
> > On Wed, Oct 19, 2016 at 09:40:16AM +0200, LABBE Corentin wrote:
> > > On Wed, Oct 05, 2016 at 12:21:30PM +0200, Jean-Francois Moine wrote:
> > > > On Wed, 5 Oct
Hi,
On Sun, Oct 23, 2016 at 09:45:03AM +0200, Jean-Francois Moine wrote:
> On Sun, 23 Oct 2016 09:33:16 +0800
> Chen-Yu Tsai wrote:
>
> > > Note: This driver is closed to the sun4i-i2s except that:
> > > - it handles the H3
> >
> > If it's close to sun4i-i2s, you should probably
Hi,
On Fri, Oct 21, 2016 at 09:26:18AM +0200, Jean-Francois Moine wrote:
> Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
> engine, DE2.
> This patch adds a DRM video driver for this device.
>
> Signed-off-by: Jean-Francois Moine
Output from checkpatch:
On Fri, Oct 21, 2016 at 11:57:11PM +0100, André Przywara wrote:
> Salut,
>
> On 11/10/16 15:28, Maxime Ripard wrote:
> > Modify the current clocks we have to be able to specify the minimum for
> > each clocks we support, just like we support the max.
> >
> > Signed-off-by: Maxime Ripard
Hi.
On Fri, 21 Oct 2016 03:19:46 -0700 (PDT) Milos Ladni
wrote:
> Hi everyone,
>
> Because there are PoC of hardware JPEG encoding and decoding, i am
> now interesting of hw scaling..
> Does does anyone tried to scale image (raw yuv 4:2:2 4:2:0 or rgb)
> with A20
Dne 24.10.2016 v 05:59 Icenowy Zheng napsal(a):
> Allwinner SoC's PHY 0, when used as OTG controller, have no pmu part.
> The code that poke some unknown bit of PMU for H3/A64 didn't check
> the PHY, and will cause kernel oops when PHY 0 is used.
>
> Fixes: b3e0d141ca9f (phy: sun4i: add support
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