Re: [linux-sunxi] Re: [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)

2016-10-29 Thread Chen-Yu Tsai 
On Sat, Oct 29, 2016 at 8:06 PM, Hans de Goede  wrote:
> Hi,
>
>
> On 28-10-16 19:30, Hans de Goede wrote:
>>
>> Hi Chen-Yu,
>>
>> On 28-10-16 12:21, Chen-Yu Tsai wrote:
>>>
>>> Hi everyone,
>>>
>>> This series adds full SPL with DRAM initialization for sun9i (A80).
>>> The bulk of the work was done by the people at Theobroma Systems.
>>> Their work can be found here:
>>>
>>> https://git.theobroma-systems.com/armadillo-u-boot.git/
>>>
>>> I picked the essential patches and cleaned them up a bit more,
>>> and added commit messages if they were missing.
>>>
>>> As the DRAM bits are essentially a code dump with some cleanups and
>>> some bits disabled, expect many warnings. Checkpatch is still not
>>> happy with it.
>>>
>>> I've tested the series on both my A80 boards, which I've added
>>> defconfigs for in the last 2 patches. My A80 Optimus does not
>>> boot from micro SD, so I'm still FEL booting that one. But my
>>> Cubieboard 4 is now standalone.
>>>
>>> As usual, please have a look, test if possible.
>>
>>
>> Awesome, thanks for doing this and it was good to have
>> some face2face time at ELCE.
>>
>> I've merged this into my personal sunxi-wip u-boot branch,
>> I've made 2 changes:
>>
>> 1) in : ¨sunxi: DRAM initialisation for sun9i" there are a
>> lot of #if 0 #endif blocks, most of these document some features
>> which we may want to enable in the future, but a few were just
>> dead weight IMHO, so I've pruned a few
>>
>> 2) in : "sunxi: Add support for A80 Optimus board", we already
>> have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch
>> update that instead of adding a new defconfig
>>
>> I have not tested this yet, I will do tomorrow, assuming it
>> works for me too I will include it in my next pull-req (*)
>
>
> Ok, just finished testing, u-boot seems to work well. I do
> seem to have one kernel issue (with the last 4.8 based
> sunxi-next kernel, I still need to upgrade that) :
>
> [1.137105] Division by zero in kernel.
> [1.140988] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0+ #475
> [1.147089] Hardware name: Allwinner sun9i Family
> [1.151830] [] (unwind_backtrace) from []
> (show_stack+0x18/0x1c)
> [1.159596] [] (show_stack) from []
> (dump_stack+0x80/0x9c)
> [1.166839] [] (dump_stack) from [] (Ldiv0+0x8/0x10)
> [1.173558] [] (Ldiv0) from []
> (sun4i_a10_get_mod0_factors+0x2c/0x8c)
> [1.181758] [] (sun4i_a10_get_mod0_factors) from []
> (clk_factors_determine_rate+0xb8/0xf8)
> [1.191781] [] (clk_factors_determine_rate) from []
> (clk_composite_determine_rate+0x58/0x1cc)
> [1.202062] [] (clk_composite_determine_rate) from []
> (clk_calc_new_rates+0xa0/0x240)
> [1.211647] [] (clk_calc_new_rates) from []
> (clk_core_set_rate_nolock+0x4c/0xbc)
> [1.220798] [] (clk_core_set_rate_nolock) from []
> (clk_set_rate+0x28/0x38)
> [1.229432] [] (clk_set_rate) from []
> (sunxi_ir_probe+0xfc/0x480)
> [1.420454] [] (sunxi_ir_probe) from []
> (platform_drv_pro
> be+0x58/0xa4)
>
> ...
>
> And it fails to find any mmc controllers, but that might be related to
> the above oops (maybe it stops probing after that due to a stuck lock).

This is related to the regulators, specifically cold boot default
values for ldo_ios causing the regulators to fail to register. You
actually fixed this for the axp22x's before.

There's also the addressing issue for the axp806.

See the top of https://github.com/wens/linux/commits/sun9i-gmac-wifi
for the bunch of fixes I need to send.

> Anyways the u-boot side looks good. One issue I see is that your
> optimus has an emmc, where as mine has a nand. We may want to
> gave 2 optimus defconfigs for this once we've nand support.

Hmm... This implies the need for 2 versions of dts files as well.
Any ideas on probing for nand/emmc during boot?

Regards
ChenYu

> Regards,
>
> Hans
>
>
>
>> and try to get it included in the 2016.11 release, yes the merge
>> window has closed, but the changes here are very isolated so
>> I will try and see what Tom says :)
>>
>> Regards,
>>
>> Hans
>>
>>
>> *) Which I hope to send out this weekend
>>
>>
>>
>>>
>>>
>>> Regards
>>> ChenYu
>>>
>>>
>>> Chen-Yu Tsai (5):
>>>   sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
>>>   sunxi: Add support for SID e-fuses on sun9i
>>>   sunxi: Add default zq value for sun9i (A80)
>>>   sunxi: Add support for A80 Optimus board
>>>   sunxi: Add support for Cubieboard4
>>>
>>> Philipp Tomsich (6):
>>>   sunxi: DRAM initialisation for sun9i
>>>   sunxi: add gtbus-initialisation for sun9i
>>>   sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
>>>   sunxi: add initial clock setup for sun9i for SPL
>>>   sunxi: enable SPL for sun9i
>>>   sunxi: add MMC pinmux setup for SDC2 on sun9i
>>>
>>>  arch/arm/include/asm/arch-sunxi/clock_sun9i.h |  116 ++-
>>>  arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |   10 +
>>>  arch/arm/include/asm/arch-sunxi/dram.h|2 +
>>>

[linux-sunxi] Re: [PATCH 01/14] dma: sun6i-dma: Add burst case of 4

2016-10-29 Thread Chen-Yu Tsai 
Hi,

On Fri, Oct 28, 2016 at 1:51 AM, Maxime Ripard
 wrote:
> On Sun, Oct 23, 2016 at 06:31:07PM +0200, Jean-Francois Moine wrote:
>> On Tue, 4 Oct 2016 18:55:54 +0200
>> Maxime Ripard  wrote:
>>
>> > On Tue, Oct 04, 2016 at 12:40:11PM +0200, Jean-Francois Moine wrote:
>> > > On Tue,  4 Oct 2016 11:46:14 +0200
>> > > Mylène Josserand  wrote:
>> > >
>> > > > Add the case of a burst of 4 which is handled by the SoC.
>> > > >
>> > > > Signed-off-by: Mylène Josserand 
>> > > > ---
>> > > >  drivers/dma/sun6i-dma.c | 2 ++
>> > > >  1 file changed, 2 insertions(+)
>> > > >
>> > > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
>> > > > index 8346199..0485204 100644
>> > > > --- a/drivers/dma/sun6i-dma.c
>> > > > +++ b/drivers/dma/sun6i-dma.c
>> > > > @@ -240,6 +240,8 @@ static inline s8 convert_burst(u32 maxburst)
>> > > > switch (maxburst) {
>> > > > case 1:
>> > > > return 0;
>> > > > +   case 4:
>> > > > +   return 1;
>> > > > case 8:
>> > > > return 2;
>> > > > default:
>> > > > --
>> > > > 2.9.3
>> > >
>> > > This patch has already been rejected by Maxime in the threads
>> > >   http://www.spinics.net/lists/dmaengine/msg08610.html
>> > > and
>> > >   http://www.spinics.net/lists/dmaengine/msg08719.html
>> > >
>> > > I hope you will find the way he wants for this maxburst to be added.
>> >
>> > I was talking about something along these lines (not tested):
>>
>> I wonder why you don't submit this yourself.
>
> I thought you were the one who cared. You asked for what I had in
> mind, here it is.
>
>> > ---8<-
>> > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
>> > index 83461994e418..573ac4608293 100644
>> > --- a/drivers/dma/sun6i-dma.c
>> > +++ b/drivers/dma/sun6i-dma.c
>> > @@ -240,6 +240,8 @@ static inline s8 convert_burst(u32 maxburst)
>> > switch (maxburst) {
>> > case 1:
>> > return 0;
>> > +   case 4:
>> > +   return 1;
>> > case 8:
>> > return 2;
>> > default:
>> > @@ -1110,11 +1112,19 @@ static int sun6i_dma_probe(struct platform_device 
>> > *pdev)
>> > sdc->slave.dst_addr_widths  = 
>> > BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
>> >   
>> > BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
>> >   
>> > BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
>> > +   sdc->slave.dst_bursts   = BIT(1) | BIT(8);
>> > +   sdc->slave.src_bursts   = BIT(1) | BIT(8);
>> > sdc->slave.directions   = BIT(DMA_DEV_TO_MEM) |
>> >   BIT(DMA_MEM_TO_DEV);
>> > sdc->slave.residue_granularity  = 
>> > DMA_RESIDUE_GRANULARITY_BURST;
>> > sdc->slave.dev = >dev;
>> >
>> > +   if (of_device_is_compatible(pdev->dev.of_node,
>> > +   "allwinner,sun8i-h3-dma")) {
>> > +   sdc->slave.dst_bursts |= BIT(4);
>> > +   sdc->slave.src_bursts |= BIT(4);
>> > +   }
>> > +
>> > sdc->pchans = devm_kcalloc(>dev, sdc->cfg->nr_max_channels,
>> >sizeof(struct sun6i_pchan), GFP_KERNEL);
>> > if (!sdc->pchans)
>> > diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
>> > index cc535a478bae..f7bbec24bb58 100644
>> > --- a/include/linux/dmaengine.h
>> > +++ b/include/linux/dmaengine.h
>> > @@ -673,6 +673,8 @@ struct dma_filter {
>> >   * each type of direction, the dma controller should fill (1 <<
>> >   * ) and same should be checked by controller as well
>> >   * @max_burst: max burst capability per-transfer
>> > + * @dst_bursts: bitfield of the available burst sizes for the destination
>> > + * @src_bursts: bitfield of the available burst sizes for the source
>>
>> You did not define dst_bursts nor src_bursts.
>>
>> >   * @residue_granularity: granularity of the transfer residue reported
>> >   * by tx_status
>> >   * @device_alloc_chan_resources: allocate resources and return the
>> > @@ -800,6 +802,14 @@ struct dma_device {
>> >  static inline int dmaengine_slave_config(struct dma_chan *chan,
>> >   struct dma_slave_config *config)
>> >  {
>> > +   if (config->src_maxburst && config->device->src_bursts &&
>> > +   !(BIT(config->src_maxburst) & config->device->src_bursts))
>>
>> The maxburst may be as big as 4Kibytes, then, I am not sure that this
>> code will work!
>>
>> > +   return -EINVAL;
>> > +
>> > +   if (config->dst_maxburst && config->device->dst_bursts &&
>> > +   !(BIT(config->dst_maxburst) & config->device->dst_bursts))
>> > +   return -EINVAL;
>> > +
>> > if (chan->device->device_config)
>> > return chan->device->device_config(chan, config);
>> >

[linux-sunxi] Re: [U-Boot, 1/2] drivers: USB: OHCI: allow compilation for 64-bit targets

2016-10-29 Thread Marek Vasut 
On 10/29/2016 02:50 PM, Hans de Goede wrote:
> Hi,
> 
> On 21-10-16 03:24, Andre Przywara wrote:
>> OHCI has a known limitation of allowing only 32-bit DMA buffer
>> addresses, so we have a lot of u32 variables around, which are assigned
>> to pointers and vice versa. This obviously creates issues with 64-bit
>> systems, so the compiler complains here and there.
>> To allow compilation for 64-bit boards which use only memory below 4GB
>> anyway (and to avoid more invasive fixes), adjust some casts and types
>> and assume that the EDs and TDs are all located in the lower 4GB.
>> This fixes compilation of the OHCI driver for the Pine64.
>>
>> Signed-off-by: Andre Przywara 
> 
> Patch looks good to me:
> 
> Reviewed-by: Hans de Goede 

Applied, thanks.

Andre, it would be nice if you CC'd me on the original submission.

> Regards,
> 
> Hans
> 
> p.s.
> 
> About the ohci_writel macro changes also giving the macro parameters
> more sensible names, I believe it is fine to do this while at it and
> that this does not need to be split out.

Indeed, I am fine with it as well.

-- 
Best regards,
Marek Vasut

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[linux-sunxi] Re: [U-Boot,2/2] sunxi: A64: enable USB support

2016-10-29 Thread Hans de Goede 

Hi,

On 21-10-16 03:24, Andre Przywara wrote:

From: Amit Singh Tomar 

Mostly by adding MACH_SUN50I to some existing #ifdefs enable support
for the the HCI0 USB host controller on the A64.
Fix up some minor 64-bit hiccups on the way.
Add the bare minimum DT bits to the A64 .dtsi and enable the controllers
and the PHY on the Pine64.
This is limited to the first USB controller at the moment, which is
connected to the lower USB socket on the Pine64 board.
[Andre: remove unneeded defines, enable OHCI, add commit message]

Signed-off-by: Amit Singh Tomar 
Signed-off-by: Andre Przywara 


Other then CONFIG_USB_MAX_CONTROLLER_COUNT no longer being necessary
(it should be dropped from include/configs/sun50i.h) this patch looks
good to me and is:

Reviewed-by: Hans de Goede 

Note I cannot merged it till Marek merges the first patch in
the series, which really needs to go through the u-boot-usb tree.

Regards,

Hans



---
 arch/arm/dts/sun50i-a64-pine64-common.dtsi  | 12 
 arch/arm/dts/sun50i-a64.dtsi| 29 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  2 +-
 arch/arm/mach-sunxi/usb_phy.c   |  5 +++--
 configs/pine64_plus_defconfig   |  1 +
 drivers/usb/host/ehci-sunxi.c   |  7 ---
 drivers/usb/host/ohci-sunxi.c   |  1 +
 include/configs/sun50i.h|  5 +
 8 files changed, 56 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
index c0fde44..9ec81c6 100644
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -79,3 +79,15 @@
pinctrl-0 = <_pins>;
status = "okay";
 };
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 7d0dc76..bef0d00 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -653,5 +653,34 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   usbphy: phy@1c1b810 {
+   compatible = "allwinner,sun50i-a64-usb-phy",
+"allwinner,sun8i-a33-usb-phy";
+   reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>;
+   reg-names = "phy_ctrl", "pmu1";
+   status = "disabled";
+   #phy-cells = <1>;
+   };
+
+   ehci1: usb@01c1b000 {
+   compatible = "allwinner,sun50i-a64-ehci",
+"generic-ehci";
+   reg = <0x01c1b000 0x100>;
+   interrupts = ;
+   phys = < 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
+   ohci1: usb@01c1b400 {
+   compatible = "allwinner,sun50i-a64-ohci",
+"generic-ohci";
+   reg = <0x01c1b400 0x100>;
+   interrupts = ;
+   phys = < 1>;
+   phy-names = "usb";
+   status = "enabled";
+   };
};
 };
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 5f93830..7232f6d 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -56,7 +56,7 @@
 #define SUNXI_USB2_BASE0x01c1c000
 #endif
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-#ifdef CONFIG_MACH_SUN8I_H3
+#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
 #define SUNXI_USBPHY_BASE  0x01c19000
 #define SUNXI_USB0_BASE0x01c1a000
 #define SUNXI_USB1_BASE0x01c1b000
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index bd1bbee..278587b 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -146,12 +146,13 @@ __maybe_unused static void usb_phy_write(struct 
sunxi_usb_phy *phy, int addr,
}
 }

-#if defined CONFIG_MACH_SUN8I_H3
+#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 {
+#if defined CONFIG_MACH_SUN8I_H3
if (phy->id == 0)
clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
-
+#endif
clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
 }
 #elif defined CONFIG_MACH_SUN8I_A83T
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 6f82190..bd3e2e6 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -10,3 +10,4 @@

[linux-sunxi] Re: [U-Boot, 1/2] drivers: USB: OHCI: allow compilation for 64-bit targets

2016-10-29 Thread Hans de Goede 

Hi,

On 21-10-16 03:24, Andre Przywara wrote:

OHCI has a known limitation of allowing only 32-bit DMA buffer
addresses, so we have a lot of u32 variables around, which are assigned
to pointers and vice versa. This obviously creates issues with 64-bit
systems, so the compiler complains here and there.
To allow compilation for 64-bit boards which use only memory below 4GB
anyway (and to avoid more invasive fixes), adjust some casts and types
and assume that the EDs and TDs are all located in the lower 4GB.
This fixes compilation of the OHCI driver for the Pine64.

Signed-off-by: Andre Przywara 


Patch looks good to me:

Reviewed-by: Hans de Goede 

Regards,

Hans

p.s.

About the ohci_writel macro changes also giving the macro parameters
more sensible names, I believe it is fine to do this while at it and
that this does not need to be split out.



---
 drivers/usb/host/ohci-hcd.c   | 21 +++--
 drivers/usb/host/ohci-sunxi.c |  2 +-
 drivers/usb/host/ohci.h   | 11 +++
 3 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index ccbfc02..0f6d03e 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -682,7 +682,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
ed->hwNextED = 0;
flush_dcache_ed(ed);
if (ohci->ed_controltail == NULL)
-   ohci_writel(ed, >regs->ed_controlhead);
+   ohci_writel((uintptr_t)ed, >regs->ed_controlhead);
else
ohci->ed_controltail->hwNextED =
   m32_swap((unsigned long)ed);
@@ -700,7 +700,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
ed->hwNextED = 0;
flush_dcache_ed(ed);
if (ohci->ed_bulktail == NULL)
-   ohci_writel(ed, >regs->ed_bulkhead);
+   ohci_writel((uintptr_t)ed, >regs->ed_bulkhead);
else
ohci->ed_bulktail->hwNextED =
   m32_swap((unsigned long)ed);
@@ -753,7 +753,7 @@ static void periodic_unlink(struct ohci *ohci, volatile 
struct ed *ed,

/* ED might have been unlinked through another path */
while (*ed_p != 0) {
-   if (((struct ed *)
+   if (((struct ed *)(uintptr_t)
m32_swap((unsigned long)ed_p)) == ed) {
*ed_p = ed->hwNextED;
aligned_ed_p = (unsigned long)ed_p;
@@ -762,7 +762,7 @@ static void periodic_unlink(struct ohci *ohci, volatile 
struct ed *ed,
aligned_ed_p + ARCH_DMA_MINALIGN);
break;
}
-   ed_p = &(((struct ed *)
+   ed_p = &(((struct ed *)(uintptr_t)
 m32_swap((unsigned long)ed_p))->hwNextED);
}
}
@@ -798,7 +798,7 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
if (ohci->ed_controltail == ed) {
ohci->ed_controltail = ed->ed_prev;
} else {
-   ((ed_t *)m32_swap(
+   ((ed_t *)(uintptr_t)m32_swap(
*((__u32 *)>hwNextED)))->ed_prev = ed->ed_prev;
}
break;
@@ -819,7 +819,7 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
if (ohci->ed_bulktail == ed) {
ohci->ed_bulktail = ed->ed_prev;
} else {
-   ((ed_t *)m32_swap(
+   ((ed_t *)(uintptr_t)m32_swap(
 *((__u32 *)>hwNextED)))->ed_prev = ed->ed_prev;
}
break;
@@ -914,12 +914,13 @@ static void td_fill(ohci_t *ohci, unsigned int info,

/* fill the old dummy TD */
td = urb_priv->td [index] =
-(td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf);
+(td_t *)(uintptr_t)
+(m32_swap(urb_priv->ed->hwTailP) & ~0xf);

td->ed = urb_priv->ed;
td->next_dl_td = NULL;
td->index = index;
-   td->data = (__u32)data;
+   td->data = (uintptr_t)data;
 #ifdef OHCI_FILL_TRACE
if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
for (i = 0; i < len; i++)
@@ -1099,7 +1100,7 @@ static void check_status(td_t *td_list)
  * we reverse the reversed done-list */
 static td_t *dl_reverse_done_list(ohci_t *ohci)
 {
-   __u32 td_list_hc;
+   uintptr_t td_list_hc;
td_t *td_rev = NULL;
td_t *td_list = NULL;

@@ -1862,7 +1863,7 @@ static int hc_start(ohci_t *ohci)
ohci_writel(0,

Re: [linux-sunxi] [PATCH] arm: dts: Pine64: add Ethernet alias

2016-10-29 Thread Hans de Goede 

Hi,

On 21-10-16 02:11, Andre Przywara wrote:

The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
missing an alias entry to trigger the driver instantiation by U-Boot.
Add the line to point U-Boot to the Ethernet DT node.
This enables TFTP boot on the Pine64.

Signed-off-by: Andre Przywara 



Thank you I've applied this to my tree and will
include it in my next pull-req.

Regards,

Hans





---
 arch/arm/dts/sun50i-a64-pine64-common.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
index d5a7249..c0fde44 100644
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -46,6 +46,7 @@

aliases {
serial0 = 
+   ethernet0 = 
};

soc {



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[linux-sunxi] Re: [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)

2016-10-29 Thread Hans de Goede 

Hi,

On 29-10-16 03:16, Chen-Yu Tsai wrote:

On Sat, Oct 29, 2016 at 1:30 AM, Hans de Goede  wrote:

Hi Chen-Yu,

On 28-10-16 12:21, Chen-Yu Tsai wrote:


Hi everyone,

This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:

https://git.theobroma-systems.com/armadillo-u-boot.git/

I picked the essential patches and cleaned them up a bit more,
and added commit messages if they were missing.

As the DRAM bits are essentially a code dump with some cleanups and
some bits disabled, expect many warnings. Checkpatch is still not
happy with it.

I've tested the series on both my A80 boards, which I've added
defconfigs for in the last 2 patches. My A80 Optimus does not
boot from micro SD, so I'm still FEL booting that one. But my
Cubieboard 4 is now standalone.

As usual, please have a look, test if possible.



Awesome, thanks for doing this and it was good to have
some face2face time at ELCE.

I've merged this into my personal sunxi-wip u-boot branch,
I've made 2 changes:

1) in : ¨sunxi: DRAM initialisation for sun9i" there are a
lot of #if 0 #endif blocks, most of these document some features
which we may want to enable in the future, but a few were just
dead weight IMHO, so I've pruned a few


Thanks. I suppose some of the testing and verbose debug calls
aren't needed. Most of the #if 0 blocks within data structures
were C99 // comments that I fixed up to get checkpatch happy.

About the features, I was already half way through the clock
code cleanup when Maxime pointed me to Theobroma's repository,
so I could add and test sigma delta modulation for PLL DDR.


If you want to, I would be fine with adding that, but IIRC
we are not doing that on a number of other SoC generations
either, not sure what this would bring it us. So it is up to
you.


For the other types of DRAM we could clean it up, but there's
really no hardware to test it on.


I would not bother with this until someone with the relevant
hardware comes forward.


2) in : "sunxi: Add support for A80 Optimus board", we already
have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch
update that instead of adding a new defconfig


Cool. I didn't notice.


I have not tested this yet, I will do tomorrow, assuming it
works for me too I will include it in my next pull-req (*) and
try to get it included in the 2016.11 release, yes the merge
window has closed, but the changes here are very isolated so
I will try and see what Tom says :)


Do you need me to send a v2 addressing review comments?


No need, I've fixed everything up in my own tree.

Regards,

Hans





Thanks
ChenYu



Regards,

Hans


*) Which I hope to send out this weekend







Regards
ChenYu


Chen-Yu Tsai (5):
  sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
  sunxi: Add support for SID e-fuses on sun9i
  sunxi: Add default zq value for sun9i (A80)
  sunxi: Add support for A80 Optimus board
  sunxi: Add support for Cubieboard4

Philipp Tomsich (6):
  sunxi: DRAM initialisation for sun9i
  sunxi: add gtbus-initialisation for sun9i
  sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
  sunxi: add initial clock setup for sun9i for SPL
  sunxi: enable SPL for sun9i
  sunxi: add MMC pinmux setup for SDC2 on sun9i

 arch/arm/include/asm/arch-sunxi/clock_sun9i.h |  116 ++-
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |   10 +
 arch/arm/include/asm/arch-sunxi/dram.h|2 +
 arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
 arch/arm/include/asm/arch-sunxi/gtbus.h   |   21 +
 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h |   89 +++
 arch/arm/mach-sunxi/Makefile  |2 +
 arch/arm/mach-sunxi/board.c   |3 +-
 arch/arm/mach-sunxi/clock.c   |6 +
 arch/arm/mach-sunxi/clock_sun9i.c |  146 +++-
 arch/arm/mach-sunxi/dram_sun9i.c  | 1059
+
 arch/arm/mach-sunxi/gtbus_sun9i.c |   48 ++
 board/sunxi/Kconfig   |   10 +-
 board/sunxi/MAINTAINERS   |   10 +
 board/sunxi/board.c   |7 +
 configs/A80_Optimus_defconfig |   18 +
 configs/Cubieboard4_defconfig |   18 +
 17 files changed, 1818 insertions(+), 22 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c
 create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c
 create mode 100644 configs/A80_Optimus_defconfig
 create mode 100644 configs/Cubieboard4_defconfig





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[linux-sunxi] Re: [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)

2016-10-29 Thread Hans de Goede 

Hi,

On 28-10-16 19:30, Hans de Goede wrote:

Hi Chen-Yu,

On 28-10-16 12:21, Chen-Yu Tsai wrote:

Hi everyone,

This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:

https://git.theobroma-systems.com/armadillo-u-boot.git/

I picked the essential patches and cleaned them up a bit more,
and added commit messages if they were missing.

As the DRAM bits are essentially a code dump with some cleanups and
some bits disabled, expect many warnings. Checkpatch is still not
happy with it.

I've tested the series on both my A80 boards, which I've added
defconfigs for in the last 2 patches. My A80 Optimus does not
boot from micro SD, so I'm still FEL booting that one. But my
Cubieboard 4 is now standalone.

As usual, please have a look, test if possible.


Awesome, thanks for doing this and it was good to have
some face2face time at ELCE.

I've merged this into my personal sunxi-wip u-boot branch,
I've made 2 changes:

1) in : ¨sunxi: DRAM initialisation for sun9i" there are a
lot of #if 0 #endif blocks, most of these document some features
which we may want to enable in the future, but a few were just
dead weight IMHO, so I've pruned a few

2) in : "sunxi: Add support for A80 Optimus board", we already
have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch
update that instead of adding a new defconfig

I have not tested this yet, I will do tomorrow, assuming it
works for me too I will include it in my next pull-req (*)


Ok, just finished testing, u-boot seems to work well. I do
seem to have one kernel issue (with the last 4.8 based
sunxi-next kernel, I still need to upgrade that) :

[1.137105] Division by zero in kernel.
[1.140988] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0+ #475
[1.147089] Hardware name: Allwinner sun9i Family
[1.151830] [] (unwind_backtrace) from [] 
(show_stack+0x18/0x1c)
[1.159596] [] (show_stack) from [] 
(dump_stack+0x80/0x9c)
[1.166839] [] (dump_stack) from [] (Ldiv0+0x8/0x10)
[1.173558] [] (Ldiv0) from [] 
(sun4i_a10_get_mod0_factors+0x2c/0x8c)
[1.181758] [] (sun4i_a10_get_mod0_factors) from [] 
(clk_factors_determine_rate+0xb8/0xf8)
[1.191781] [] (clk_factors_determine_rate) from [] 
(clk_composite_determine_rate+0x58/0x1cc)
[1.202062] [] (clk_composite_determine_rate) from [] 
(clk_calc_new_rates+0xa0/0x240)
[1.211647] [] (clk_calc_new_rates) from [] 
(clk_core_set_rate_nolock+0x4c/0xbc)
[1.220798] [] (clk_core_set_rate_nolock) from [] 
(clk_set_rate+0x28/0x38)
[1.229432] [] (clk_set_rate) from [] 
(sunxi_ir_probe+0xfc/0x480)
[1.420454] [] (sunxi_ir_probe) from [] (platform_drv_pro
be+0x58/0xa4)

...

And it fails to find any mmc controllers, but that might be related to
the above oops (maybe it stops probing after that due to a stuck lock).

Anyways the u-boot side looks good. One issue I see is that your
optimus has an emmc, where as mine has a nand. We may want to
gave 2 optimus defconfigs for this once we've nand support.

Regards,

Hans



and try to get it included in the 2016.11 release, yes the merge
window has closed, but the changes here are very isolated so
I will try and see what Tom says :)

Regards,

Hans


*) Which I hope to send out this weekend






Regards
ChenYu


Chen-Yu Tsai (5):
  sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
  sunxi: Add support for SID e-fuses on sun9i
  sunxi: Add default zq value for sun9i (A80)
  sunxi: Add support for A80 Optimus board
  sunxi: Add support for Cubieboard4

Philipp Tomsich (6):
  sunxi: DRAM initialisation for sun9i
  sunxi: add gtbus-initialisation for sun9i
  sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
  sunxi: add initial clock setup for sun9i for SPL
  sunxi: enable SPL for sun9i
  sunxi: add MMC pinmux setup for SDC2 on sun9i

 arch/arm/include/asm/arch-sunxi/clock_sun9i.h |  116 ++-
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |   10 +
 arch/arm/include/asm/arch-sunxi/dram.h|2 +
 arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
 arch/arm/include/asm/arch-sunxi/gtbus.h   |   21 +
 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h |   89 +++
 arch/arm/mach-sunxi/Makefile  |2 +
 arch/arm/mach-sunxi/board.c   |3 +-
 arch/arm/mach-sunxi/clock.c   |6 +
 arch/arm/mach-sunxi/clock_sun9i.c |  146 +++-
 arch/arm/mach-sunxi/dram_sun9i.c  | 1059 +
 arch/arm/mach-sunxi/gtbus_sun9i.c |   48 ++
 board/sunxi/Kconfig   |   10 +-
 board/sunxi/MAINTAINERS   |   10 +
 board/sunxi/board.c   |7 +
 configs/A80_Optimus_defconfig |   18 +
 configs/Cubieboard4_defconfig |   18 +
 17 files changed, 1818 insertions(+), 22 deletions(-)
 create mode 100644

[linux-sunxi] Re: [U-Boot] [PATCH 02/11] sunxi: add gtbus-initialisation for sun9i

2016-10-29 Thread Hans de Goede 

Hi,

On 29-10-16 13:08, Chen-Yu Tsai wrote:

On Sat, Oct 29, 2016 at 2:45 AM, Jagan Teki  wrote:

On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai  wrote:

From: Philipp Tomsich 

On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).

Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.

[w...@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |  2 +
 arch/arm/include/asm/arch-sunxi/gtbus.h   | 21 +++
 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89 +++
 arch/arm/mach-sunxi/Makefile  |  1 +
 arch/arm/mach-sunxi/clock.c   |  6 ++
 arch/arm/mach-sunxi/gtbus_sun9i.c | 48 +++
 6 files changed, 167 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index acbc94f4c3b8..ba18a0f551ad 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -23,6 +23,8 @@
 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)

+#define SUNXI_GTBUS_BASE   (REGS_AHB0_BASE + 0x9000)
+
 #define SUNXI_MMC0_BASE(REGS_AHB0_BASE + 0x0f000)
 #define SUNXI_MMC1_BASE(REGS_AHB0_BASE + 0x1)
 #define SUNXI_MMC2_BASE(REGS_AHB0_BASE + 0x11000)
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h 
b/arch/arm/include/asm/arch-sunxi/gtbus.h
new file mode 100644
index ..b8308d513545
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus.h
@@ -0,0 +1,21 @@
+/*
+ * GTBUS initialisation
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *Philipp Tomsich 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_H
+#define _SUNXI_GTBUS_H
+
+#if defined(CONFIG_MACH_SUN9I)
+#include 
+#endif
+
+#ifndef __ASSEMBLY__
+void gtbus_init(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
new file mode 100644
index ..91bc2bdb5103
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
@@ -0,0 +1,89 @@
+/*
+ * GTBUS initialisation for sun9i
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *Philipp Tomsich 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_SUN9I_H
+#define _SUNXI_GTBUS_SUN9I_H
+
+#include 
+
+struct sunxi_gtbus_reg {
+   u32 mst_cfg[36];   /* 0x000 */
+   u8  reserved1[0x70];   /* 0x090 */
+   u32 bw_wdw_cfg;/* 0x100 */
+   u32 mst_read_prio_cfg[2];  /* 0x104 */
+   u32 lvl2_mst_cfg;  /* 0x10c */
+   u32 sw_clk_on; /* 0x110 */
+   u32 sw_clk_off;/* 0x114 */
+   u32 pmu_mst_en;/* 0x118 */
+   u32 pmu_cfg;   /* 0x11c */
+   u32 pmu_cnt[19];   /* 0x120 */
+   u32 reserved2[0x94];   /* 0x16c */
+   u32 cci400_config[3];  /* 0x200 */
+   u32 cci400_status[2];  /* 0x20c */
+};
+
+/* for register GT_MST_CFG_REG(n) */
+#define GT_ENABLE_REQ   (1<<31) /* clock on */
+#define GT_DISABLE_REQ  (1<<30) /* clock off */
+#define GT_QOS_SHIFT28
+#define GT_THD1_SHIFT   16
+#define GT_REQN_MAX 0xf /* max number master requests in one 
cycle */
+#define GT_REQN_SHIFT   12
+#define GT_THD0_SHIFT   0
+
+#define GT_QOS_MAX  0x3
+#define GT_THD_MAX  0xfff
+#define GT_BW_WDW_MAX   0x
+
+/* mst_read_prio_cfg */
+#define GT_PRIO_LOW 0
+#define GT_PRIO_HIGH1
+
+/* GTBUS port ids */
+#define GT_PORT_CPUM1   0
+#define GT_PORT_CPUM2   1
+#define GT_PORT_SATA2
+#defineGT_PORT_USB33
+#defineGT_PORT_FE0 4
+#defineGT_PORT_BE1 5
+#defineGT_PORT_BE2 6
+#defineGT_PORT_IEP07
+#defineGT_PORT_FE1 8
+#defineGT_PORT_BE0 9
+#defineGT_PORT_FE2 10
+#defineGT_PORT_IEP111
+#defineGT_PORT_VED 12
+#define

[linux-sunxi] Re: [U-Boot] [PATCH 02/11] sunxi: add gtbus-initialisation for sun9i

2016-10-29 Thread Chen-Yu Tsai 
On Sat, Oct 29, 2016 at 2:45 AM, Jagan Teki  wrote:
> On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai  wrote:
>> From: Philipp Tomsich 
>>
>> On sun9i, the GTBUS manages transaction priority and bandwidth
>> for multiple read ports when accessing DRAM. The initialisation
>> mirrors the settings from Allwinner's boot0 for now, even though
>> this may not be optimal for all applications (e.g. headless
>> systems might want to give priority to IO modules).
>>
>> Adding a common callout to gtbus_init() from the SPL clock init
>> with a weakly defined implementation in sunxi/clock.c to fallback
>> to for platforms that don't require this.
>>
>> [w...@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
>> Signed-off-by: Chen-Yu Tsai 
>> ---
>>  arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |  2 +
>>  arch/arm/include/asm/arch-sunxi/gtbus.h   | 21 +++
>>  arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89 
>> +++
>>  arch/arm/mach-sunxi/Makefile  |  1 +
>>  arch/arm/mach-sunxi/clock.c   |  6 ++
>>  arch/arm/mach-sunxi/gtbus_sun9i.c | 48 +++
>>  6 files changed, 167 insertions(+)
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
>>  create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h 
>> b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
>> index acbc94f4c3b8..ba18a0f551ad 100644
>> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
>> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
>> @@ -23,6 +23,8 @@
>>  #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
>>  #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
>>
>> +#define SUNXI_GTBUS_BASE   (REGS_AHB0_BASE + 0x9000)
>> +
>>  #define SUNXI_MMC0_BASE(REGS_AHB0_BASE + 0x0f000)
>>  #define SUNXI_MMC1_BASE(REGS_AHB0_BASE + 0x1)
>>  #define SUNXI_MMC2_BASE(REGS_AHB0_BASE + 0x11000)
>> diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h 
>> b/arch/arm/include/asm/arch-sunxi/gtbus.h
>> new file mode 100644
>> index ..b8308d513545
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-sunxi/gtbus.h
>> @@ -0,0 +1,21 @@
>> +/*
>> + * GTBUS initialisation
>> + *
>> + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
>> + *Philipp Tomsich 
>> 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#ifndef _SUNXI_GTBUS_H
>> +#define _SUNXI_GTBUS_H
>> +
>> +#if defined(CONFIG_MACH_SUN9I)
>> +#include 
>> +#endif
>> +
>> +#ifndef __ASSEMBLY__
>> +void gtbus_init(void);
>> +#endif
>> +
>> +#endif
>> diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h 
>> b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
>> new file mode 100644
>> index ..91bc2bdb5103
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
>> @@ -0,0 +1,89 @@
>> +/*
>> + * GTBUS initialisation for sun9i
>> + *
>> + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
>> + *Philipp Tomsich 
>> 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#ifndef _SUNXI_GTBUS_SUN9I_H
>> +#define _SUNXI_GTBUS_SUN9I_H
>> +
>> +#include 
>> +
>> +struct sunxi_gtbus_reg {
>> +   u32 mst_cfg[36];   /* 0x000 */
>> +   u8  reserved1[0x70];   /* 0x090 */
>> +   u32 bw_wdw_cfg;/* 0x100 */
>> +   u32 mst_read_prio_cfg[2];  /* 0x104 */
>> +   u32 lvl2_mst_cfg;  /* 0x10c */
>> +   u32 sw_clk_on; /* 0x110 */
>> +   u32 sw_clk_off;/* 0x114 */
>> +   u32 pmu_mst_en;/* 0x118 */
>> +   u32 pmu_cfg;   /* 0x11c */
>> +   u32 pmu_cnt[19];   /* 0x120 */
>> +   u32 reserved2[0x94];   /* 0x16c */
>> +   u32 cci400_config[3];  /* 0x200 */
>> +   u32 cci400_status[2];  /* 0x20c */
>> +};
>> +
>> +/* for register GT_MST_CFG_REG(n) */
>> +#define GT_ENABLE_REQ   (1<<31) /* clock on */
>> +#define GT_DISABLE_REQ  (1<<30) /* clock off */
>> +#define GT_QOS_SHIFT28
>> +#define GT_THD1_SHIFT   16
>> +#define GT_REQN_MAX 0xf /* max number master requests in 
>> one cycle */
>> +#define GT_REQN_SHIFT   12
>> +#define GT_THD0_SHIFT   0
>> +
>> +#define GT_QOS_MAX  0x3
>> +#define GT_THD_MAX  0xfff
>> +#define GT_BW_WDW_MAX   0x
>> +
>> +/* mst_read_prio_cfg */
>> +#define GT_PRIO_LOW 0
>> +#define GT_PRIO_HIGH1
>> +
>> +/* GTBUS port ids */
>> +#define GT_PORT_CPUM1   0
>> +#define GT_PORT_CPUM2   1
>> +#define GT_PORT_SATA2
>>

[linux-sunxi] [PATCH v3 1/2] drm/bridge: dumb-vga-dac: Support a VDD regulator supply

2016-10-29 Thread Chen-Yu Tsai 
Some dumb VGA DACs are active components which require external power.
Add support for specifying a regulator as its power supply.

Signed-off-by: Chen-Yu Tsai 
---
 .../bindings/display/bridge/dumb-vga-dac.txt   |  2 ++
 drivers/gpu/drm/bridge/dumb-vga-dac.c  | 35 ++
 2 files changed, 37 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt 
b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
index 003bc246a270..164cbb15f04c 100644
--- a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
+++ b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
@@ -16,6 +16,8 @@ graph bindings specified in 
Documentation/devicetree/bindings/graph.txt.
 - Video port 0 for RGB input
 - Video port 1 for VGA output
 
+Optional properties:
+- vdd-supply: Power supply for DAC
 
 Example
 ---
diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c 
b/drivers/gpu/drm/bridge/dumb-vga-dac.c
index afec232185a7..59781e031220 100644
--- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
+++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
@@ -12,6 +12,7 @@
 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -23,6 +24,7 @@ struct dumb_vga {
struct drm_connectorconnector;
 
struct i2c_adapter  *ddc;
+   struct regulator*vdd;
 };
 
 static inline struct dumb_vga *
@@ -124,8 +126,33 @@ static int dumb_vga_attach(struct drm_bridge *bridge)
return 0;
 }
 
+static void dumb_vga_enable(struct drm_bridge *bridge)
+{
+   struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
+   int ret;
+
+   if (!IS_ERR(vga->vdd)) {
+   ret = regulator_enable(vga->vdd);
+
+   if (ret) {
+   DRM_ERROR("Failed to enable vdd regulator: %d\n", ret);
+   return;
+   }
+   }
+}
+
+static void dumb_vga_disable(struct drm_bridge *bridge)
+{
+   struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
+
+   if (!IS_ERR(vga->vdd))
+   regulator_disable(vga->vdd);
+}
+
 static const struct drm_bridge_funcs dumb_vga_bridge_funcs = {
.attach = dumb_vga_attach,
+   .enable = dumb_vga_enable,
+   .disable= dumb_vga_disable,
 };
 
 static struct i2c_adapter *dumb_vga_retrieve_ddc(struct device *dev)
@@ -169,6 +196,14 @@ static int dumb_vga_probe(struct platform_device *pdev)
return -ENOMEM;
platform_set_drvdata(pdev, vga);
 
+   vga->vdd = devm_regulator_get_optional(>dev, "vdd");
+   if (IS_ERR(vga->vdd)) {
+   ret = PTR_ERR(vga->vdd);
+   if (ret == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   dev_dbg(>dev, "No vdd regulator found: %d\n", ret);
+   }
+
vga->ddc = dumb_vga_retrieve_ddc(>dev);
if (IS_ERR(vga->ddc)) {
if (PTR_ERR(vga->ddc) == -ENODEV) {
-- 
2.9.3

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[linux-sunxi] [PATCH v3 2/2] ARM: dts: sun6i: hummingbird-a31: Enable display output through VGA bridge

2016-10-29 Thread Chen-Yu Tsai 
The Hummingbird A31 board has a VGA DAC which converts RGB output
from the LCD interface to VGA analog signals.

Add nodes for the VGA DAC, its power supply, and enable this part
of the display pipeline.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 76 +
 1 file changed, 76 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts 
b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index 9a74637f677f..1ab28b2108fe 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -63,6 +63,62 @@
stdout-path = "serial0:115200n8";
};
 
+   vga-connector {
+   compatible = "vga-connector";
+
+   port {
+   vga_con_in: endpoint {
+   remote-endpoint = <_dac_out>;
+   };
+   };
+   };
+
+   vga-dac {
+   compatible = "dumb-vga-dac";
+   vdd-supply = <_vga_3v3>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   vga_dac_in: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_out_vga>;
+   };
+   };
+
+   port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   vga_dac_out: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_con_in>;
+   };
+   };
+   };
+   };
+
+   reg_vga_3v3: vga_3v3_regulator {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <_3v3_enable_pin_hummingbird>;
+   regulator-name = "vga-3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   enable-active-high;
+   gpio = < 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */
+   };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 */
@@ -166,6 +222,13 @@
allwinner,pull = ;
};
 
+   vga_3v3_enable_pin_hummingbird: vga_3v3_enable_pin {
+   allwinner,pins = "PH25";
+   allwinner,function = "gpio_out";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
wifi_reset_pin_hummingbird: wifi_reset_pin@0 {
allwinner,pins = "PG10";
allwinner,function = "gpio_out";
@@ -245,6 +308,19 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_rgb888_pins>;
+   status = "okay";
+};
+
+_out {
+   tcon0_out_vga: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_dac_in>;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.9.3

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[linux-sunxi] Re: [U-Boot] [PATCH 01/11] sunxi: DRAM initialisation for sun9i

2016-10-29 Thread Chen-Yu Tsai 
On Sat, Oct 29, 2016 at 6:39 PM, Hans de Goede  wrote:
> Hi,
>
> On 28-10-16 20:54, Jagan Teki wrote:
>>
>> On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai  wrote:
>>>
>>> From: Philipp Tomsich 
>>>
>>> This adds DRAM initialisation code for sun9i, which calculates the
>>> appropriate timings based on timing information for the supplied
>>> DDR3 bin and the clock speeds used.
>>>
>>> With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
>>> (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
>>>
>>> [w...@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style
>>> cleanup]
>>> Signed-off-by: Chen-Yu Tsai 
>>> ---
>>>  arch/arm/include/asm/arch-sunxi/clock_sun9i.h |   34 +-
>>>  arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |6 +
>>>  arch/arm/include/asm/arch-sunxi/dram.h|2 +
>>>  arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
>>>  arch/arm/mach-sunxi/Makefile  |1 +
>>>  arch/arm/mach-sunxi/dram_sun9i.c  | 1059
>>> +
>>>  board/sunxi/Kconfig   |6 +-
>>>  7 files changed, 1368 insertions(+), 15 deletions(-)
>>>  create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
>>>  create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c
>>
>>
>> Checkpatch:
>> total: 45 errors, 77 warnings, 42 checks, 1464 lines checked
>
>
> Ugh, ok I've fixed this up locally in my tree, Chen-Yu next time
> please remember to run your patches through check-patch.

Sorry about that. Checkpatch considers #if 0 dead code, but the
reality is that a lot of the marked code may or may not be used
later. We just don't know. A lot of it was marked with C99 style
( // ) comments. Using #if 0 is easier to retain trailing comments
within the currently unused sections. Switching to traditional
C style comments means we might be editing those same lines again.

Otherwise I think I cleaned up most of the 'used' code.

Regards
ChenYu

> Jagan, thanks for the review I've addressed all your comments
> in my tree.
>
> Regards,
>
> Hans
>
>
>
>>
>>>
>>> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
>>> b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
>>> index a61934fb3661..82881ff8bdaf 100644
>>> --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
>>> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
>>> @@ -37,57 +37,61 @@ struct sunxi_ccm_reg {
>>> u8 reserved3[0x04]; /* 0x7c */
>>> u32 ats_cfg;/* 0x80 ats clock configuration */
>>> u32 trace_cfg;  /* 0x84 trace clock configuration */
>>> -   u8 reserved4[0xf8]; /* 0x88 */
>>> +   u8 reserved4[0x14]; /* 0x88 */
>>> +   u32 pll_stable_status;  /* 0x9c */
>>> +   u8 reserved5[0xe0]; /* 0xa0 */
>>> u32 clk_output_a;   /* 0x180 clk_output_a */
>>> u32 clk_output_b;   /* 0x184 clk_output_a */
>>> -   u8 reserved5[0x278];/* 0x188 */
>>> +   u8 reserved6[0x278];/* 0x188 */
>>>
>>> u32 nand0_clk_cfg;  /* 0x400 nand0 clock configuration0 */
>>> u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
>>> -   u8 reserved6[0x08]; /* 0x408 */
>>> +   u8 reserved7[0x08]; /* 0x408 */
>>> u32 sd0_clk_cfg;/* 0x410 sd0 clock configuration */
>>> u32 sd1_clk_cfg;/* 0x414 sd1 clock configuration */
>>> u32 sd2_clk_cfg;/* 0x418 sd2 clock configuration */
>>> u32 sd3_clk_cfg;/* 0x41c sd3 clock configuration */
>>> -   u8 reserved7[0x08]; /* 0x420 */
>>> +   u8 reserved8[0x08]; /* 0x420 */
>>> u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
>>> u32 ss_clk_cfg; /* 0x42c security system clock cfg */
>>> u32 spi0_clk_cfg;   /* 0x430 spi0 clock configuration */
>>> u32 spi1_clk_cfg;   /* 0x434 spi1 clock configuration */
>>> u32 spi2_clk_cfg;   /* 0x438 spi2 clock configuration */
>>> u32 spi3_clk_cfg;   /* 0x43c spi3 clock configuration */
>>> -   u8 reserved8[0x50]; /* 0x440 */
>>> +   u8 reserved9[0x44]; /* 0x440 */
>>> +   u32 dram_clk_cfg;   /* 0x484 DRAM (controller) clock
>>> configuration */
>>> +   u8 reserved10[0x8]; /* 0x488 */
>>> u32 de_clk_cfg; /* 0x490 display engine clock
>>> configuration */
>>> -   u8 reserved9[0x04]; /* 0x494 */
>>> +   u8 reserved11[0x04];/* 0x494 */
>>> u32 mp_clk_cfg; /* 0x498 mp clock configuration */
>>> u32 lcd0_clk_cfg;   /* 0x49c LCD0 module clock */
>>> u32 lcd1_clk_cfg;   /* 0x4a0 LCD1 module clock */
>>> -   u8 reserved10[0x1c];/* 0x4a4 */
>>> +   u8 reserved12[0x1c];/* 0x4a4 */
>>> u32 csi_isp_clk_cfg;/* 0x4c0 CSI ISP module clock */
>>> u32 csi0_clk_cfg;   /* 0x4c4 CSI0

[linux-sunxi] Re: [U-Boot] [PATCH 01/11] sunxi: DRAM initialisation for sun9i

2016-10-29 Thread Hans de Goede 

Hi,

On 28-10-16 20:54, Jagan Teki wrote:

On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai  wrote:

From: Philipp Tomsich 

This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.

With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.

[w...@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/clock_sun9i.h |   34 +-
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |6 +
 arch/arm/include/asm/arch-sunxi/dram.h|2 +
 arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
 arch/arm/mach-sunxi/Makefile  |1 +
 arch/arm/mach-sunxi/dram_sun9i.c  | 1059 +
 board/sunxi/Kconfig   |6 +-
 7 files changed, 1368 insertions(+), 15 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c


Checkpatch:
total: 45 errors, 77 warnings, 42 checks, 1464 lines checked


Ugh, ok I've fixed this up locally in my tree, Chen-Yu next time
please remember to run your patches through check-patch.

Jagan, thanks for the review I've addressed all your comments
in my tree.

Regards,

Hans







diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index a61934fb3661..82881ff8bdaf 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -37,57 +37,61 @@ struct sunxi_ccm_reg {
u8 reserved3[0x04]; /* 0x7c */
u32 ats_cfg;/* 0x80 ats clock configuration */
u32 trace_cfg;  /* 0x84 trace clock configuration */
-   u8 reserved4[0xf8]; /* 0x88 */
+   u8 reserved4[0x14]; /* 0x88 */
+   u32 pll_stable_status;  /* 0x9c */
+   u8 reserved5[0xe0]; /* 0xa0 */
u32 clk_output_a;   /* 0x180 clk_output_a */
u32 clk_output_b;   /* 0x184 clk_output_a */
-   u8 reserved5[0x278];/* 0x188 */
+   u8 reserved6[0x278];/* 0x188 */

u32 nand0_clk_cfg;  /* 0x400 nand0 clock configuration0 */
u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
-   u8 reserved6[0x08]; /* 0x408 */
+   u8 reserved7[0x08]; /* 0x408 */
u32 sd0_clk_cfg;/* 0x410 sd0 clock configuration */
u32 sd1_clk_cfg;/* 0x414 sd1 clock configuration */
u32 sd2_clk_cfg;/* 0x418 sd2 clock configuration */
u32 sd3_clk_cfg;/* 0x41c sd3 clock configuration */
-   u8 reserved7[0x08]; /* 0x420 */
+   u8 reserved8[0x08]; /* 0x420 */
u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
u32 ss_clk_cfg; /* 0x42c security system clock cfg */
u32 spi0_clk_cfg;   /* 0x430 spi0 clock configuration */
u32 spi1_clk_cfg;   /* 0x434 spi1 clock configuration */
u32 spi2_clk_cfg;   /* 0x438 spi2 clock configuration */
u32 spi3_clk_cfg;   /* 0x43c spi3 clock configuration */
-   u8 reserved8[0x50]; /* 0x440 */
+   u8 reserved9[0x44]; /* 0x440 */
+   u32 dram_clk_cfg;   /* 0x484 DRAM (controller) clock configuration 
*/
+   u8 reserved10[0x8]; /* 0x488 */
u32 de_clk_cfg; /* 0x490 display engine clock configuration */
-   u8 reserved9[0x04]; /* 0x494 */
+   u8 reserved11[0x04];/* 0x494 */
u32 mp_clk_cfg; /* 0x498 mp clock configuration */
u32 lcd0_clk_cfg;   /* 0x49c LCD0 module clock */
u32 lcd1_clk_cfg;   /* 0x4a0 LCD1 module clock */
-   u8 reserved10[0x1c];/* 0x4a4 */
+   u8 reserved12[0x1c];/* 0x4a4 */
u32 csi_isp_clk_cfg;/* 0x4c0 CSI ISP module clock */
u32 csi0_clk_cfg;   /* 0x4c4 CSI0 module clock */
u32 csi1_clk_cfg;   /* 0x4c8 CSI1 module clock */
u32 fd_clk_cfg; /* 0x4cc FD module clock */
u32 ve_clk_cfg; /* 0x4d0 VE module clock */
u32 avs_clk_cfg;/* 0x4d4 AVS module clock */
-   u8 reserved11[0x18];/* 0x4d8 */
+   u8 reserved13[0x18];/* 0x4d8 */
u32 gpu_core_clk_cfg;   /* 0x4f0 GPU core clock config */
u32 gpu_mem_clk_cfg;/* 0x4f4 GPU memory clock config */
u32 gpu_axi_clk_cfg;/* 0x4f8 GPU AXI clock config */
-   u8 reserved12[0x10];/* 0x4fc */
+   u8 reserved14[0x10];/* 0x4fc */
u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
-   u8 reserved13[0x70];/* 0x510 */
+   u8 reserved15[0x70];/* 0x510 */

u32 ahb_gate0;  /* 0x580 AHB0 Gating Register */
u32