[linux-sunxi] Re: [PATCH v2 1/2] nvmem: sunxi-sid: add support for H3 and A64's SID controller

On Sun, Jan 29, 2017 at 09:56:40AM +0800, Icenowy Zheng wrote: > H3 and A64 SoCs have a bigger SID controller, which has its direct read > address at 0x200 position in the SID block, not 0x0. > > Also, H3 SID controller has some silicon bug that makes the direct read > value wrong at first, add

[linux-sunxi] Re: [PATCH v2 00/10] clk: sunxi-ng: Add support for A80 CCUs

Hi, On Sat, Jan 28, 2017 at 08:22:29PM +0800, Chen-Yu Tsai wrote: > Hi everyone, > > This is v2 of my A80 CCU clk patches. Changes since v1: > > - Use pre-divider adjusted parent rate for rounding. > > - Use else statement for the case where the PLL lock status bit is > in same

[linux-sunxi] Re: [PATCH v3 05/10] arm: dts: sun8i: split Allwinner H3 .dtsi

On 29/01/17 02:33, Icenowy Zheng wrote: > From: Andre Przywara (Adding DT folks to CC:) see below ... > The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the > Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller > updated. So we should