Re: [linux-sunxi] [PATCH v3 0/5] Add dual-role OTG support for Allwinner H3

On Tue, Mar 7, 2017 at 8:24 AM, Icenowy Zheng wrote: > > > 07.03.2017, 07:48, "Ondřej Jirman" : >> Hi Icenowy, >> >> when I was trying to add OTG support I found an issue with powercycling. >> When I have USB cable connecting PC and the OTG port on the SBC,

Re: [linux-sunxi] [PATCH v3 0/5] Add dual-role OTG support for Allwinner H3

07.03.2017, 07:48, "Ondřej Jirman" : > Hi Icenowy, > > when I was trying to add OTG support I found an issue with powercycling. > When I have USB cable connecting PC and the OTG port on the SBC, when > the board enables the vbus, it would become impossible to power cycle > the

[linux-sunxi] Re: [alsa-devel] [PATCH v2 03/12] ASoC: sun8i-codec-analog: split out mbias

Hi Icenowy, [auto build test ERROR on linus/master] [also build test ERROR on v4.11-rc1 next-20170306] [cannot apply to robh/for-next asoc/for-next] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux

Re: [linux-sunxi] [PATCH v3 0/5] Add dual-role OTG support for Allwinner H3

Hi Icenowy, when I was trying to add OTG support I found an issue with powercycling. When I have USB cable connecting PC and the OTG port on the SBC, when the board enables the vbus, it would become impossible to power cycle the board after poweroff. The reason being that when vbus is enabled,

[linux-sunxi] [PATCH v3 5/5] ARM: dts: sun8i: h2+: enable USB OTG for Orange Pi Zero board

Orange Pi Zero board features a USB OTG port, which has a ID pin, and can be used to power up the board. However, even if the board is powered via +5V pin in GPIO/expansion headers, the VBUS in the OTG port cannot be powered up, thus it's impossible to use it in host mode with simple OTG cables.

[linux-sunxi] [PATCH v3 4/5] ARM: dts: sun8i: h3: enable USB OTG on Orange Pi One

Orange Pi One features a MicroUSB port that can work in both host mode and peripheral mode. When in host mode, its VBUS is controlled via a GPIO; when in peripheral mode, its VBUS cannot be used to power up the board. Add support for this port. Signed-off-by: Icenowy Zheng

[linux-sunxi] [PATCH v3 1/5] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allwinner SoCs. Add this to the binding of USB PHYs on

[linux-sunxi] [PATCH v3 2/5] phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI

On newer Allwinner SoCs (H3 and after), the PHY0 node is routed to both MUSB controller for peripheral and host support (the host support is slightly broken), and a pair of EHCI/OHCI controllers, which provide a better support for host mode. Add support for automatically switch the route of PHY0

[linux-sunxi] [PATCH v3 0/5] Add dual-role OTG support for Allwinner H3

Allwinner H3 have a its USB PHY0 routed to two USB controllers: one is a MUSB controller, which can work in peripheral mode, but works badly in host mode (several hardware will fail on the MUSB controller, even connect one MUSB controller in peripheral mode to another one in host mode cannot

Re: [linux-sunxi] Re: PoC tvin2jpeg_h264 with veisp scaling

On Mon, 6 Mar 2017 00:51:08 -0800 (PST) Milos Ladni wrote: > Hi, > > > What i can suggest you to do is to make an experience, to check if > > the hardware is been correctly configured for each task. > > > > Before selecting the subengine for each task change, to do a

[linux-sunxi] [PATCH v8 6/6] arm64: dts: allwinner: h5: add support for the Orange Pi PC 2 board

From: Andre Przywara The Orange Pi PC 2 is a typical single board computer using the Allwinner H5 SoC. Apart from the usual suspects it features three separately driven USB ports and a Gigabit Ethernet port. Also it has a SPI NOR flash soldered, from which the board can

[linux-sunxi] [PATCH v8 5/6] arm64: dts: allwinner: h5: add Allwinner H5 .dtsi

From: Andre Przywara The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses Cortex-A53 cores instead. Based on the now shared base .dtsi describing the common peripherals describe the H5 specific nodes on top of that. That symlinks in the sunxi-h3-h5.dtsi from the

[linux-sunxi] [PATCH v8 3/6] ARM: dts: sun8i: h3: correct the GIC compatible in H3 to gic-400

According to the datasheets provided by Allwinner, both Allwinner H3 and H5 use GIC-400 as their interrupt controller. For better device tree reusing, correct the GIC compatible in H3 DTSI to "arm,gic-400", thus this node can be reused in H5. Signed-off-by: Icenowy Zheng ---

[linux-sunxi] [PATCH v8 2/6] ARM: dts: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI

After converting to generic pinconf binding, pinctrl-a10.h is now not used at all. Drop its inclusion for H3 DTSI. Signed-off-by: Icenowy Zheng --- Changes in v8: - Add h3: in commit message. arch/arm/boot/dts/sun8i-h3.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git

[linux-sunxi] [PATCH v8 1/6] ARM: dts: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI

The skeleton.dtsi file is now deprecated, and do not exist in ARM64 environment. Since we will soon reuse most part of H3 DTSI for H5, which is an ARM64 chip, drop skeleton.dtsi inclusion now. Signed-off-by: Icenowy Zheng --- Changes in v8: - Add h3: in commit message.

[linux-sunxi] [PATCH v8 0/6] Allwinner H5 and Orange Pi PC2 support

Allwinner H5 is a 64-bit SoC with a design like the 32-bit H3, and it's pin-to-pin compatible with H3. This patchset adds support for it, along with the first available board -- Orange Pi PC2. Several H5 boards by Sinovoip Banana Pi and FriendlyARM Nano Pi are coming, so we should get ready for

Re: [linux-sunxi] Re: [PATCH 14/17] sunxi: Pine64: defconfig: enable SPL FIT support

On Mon, Mar 06, 2017 at 03:11:29PM +, Andre Przywara wrote: > Hi, > > On 06/03/17 10:00, Maxime Ripard wrote: > > On Fri, Mar 03, 2017 at 09:55:25AM +, Andre Przywara wrote: > >> Hi, > >> > >> On 03/03/17 09:22, Maxime Ripard wrote: > >>> On Thu, Mar 02, 2017 at 12:03:20AM +0800, Icenowy

Re: [linux-sunxi] Re: [PATCH 14/17] sunxi: Pine64: defconfig: enable SPL FIT support

Hi, On 06/03/17 10:00, Maxime Ripard wrote: > On Fri, Mar 03, 2017 at 09:55:25AM +, Andre Przywara wrote: >> Hi, >> >> On 03/03/17 09:22, Maxime Ripard wrote: >>> On Thu, Mar 02, 2017 at 12:03:20AM +0800, Icenowy Zheng wrote: 2017年3月1日 23:51于 Maxime Ripard

Re: [linux-sunxi] Re: [PATCH v7 1/6] ARM: dts: sun8i: drop skeleton.dtsi inclusion in H3 DTSI

On Mon, Mar 6, 2017 at 6:46 PM, Icenowy Zheng wrote: > > > 06.03.2017, 18:35, "Maxime Ripard" : >> Hi, >> >> On Mon, Mar 06, 2017 at 07:31:33AM +0800, Icenowy Zheng wrote: >>> The skeleton.dtsi file is now deprecated, and do not exist in ARM64

[linux-sunxi] Re: [PATCH v7 1/6] ARM: dts: sun8i: drop skeleton.dtsi inclusion in H3 DTSI

06.03.2017, 18:35, "Maxime Ripard" : > Hi, > > On Mon, Mar 06, 2017 at 07:31:33AM +0800, Icenowy Zheng wrote: >>  The skeleton.dtsi file is now deprecated, and do not exist in ARM64 >>  environment. >> >>  Since we will soon reuse most part of H3 DTSI for H5,

[linux-sunxi] Re: [PATCH v7 6/6] arm64: dts: sunxi: add support for the Orange Pi PC 2 board

On Mon, Mar 06, 2017 at 07:31:38AM +0800, Icenowy Zheng wrote: > From: Andre Przywara > > The Orange Pi PC 2 is a typical single board computer using the > Allwinner H5 SoC. Apart from the usual suspects it features three > separately driven USB ports and a Gigabit

Re: [linux-sunxi] Re: [PATCH 14/17] sunxi: Pine64: defconfig: enable SPL FIT support

On Fri, Mar 03, 2017 at 09:55:25AM +, Andre Przywara wrote: > Hi, > > On 03/03/17 09:22, Maxime Ripard wrote: > > On Thu, Mar 02, 2017 at 12:03:20AM +0800, Icenowy Zheng wrote: > >> > >> 2017年3月1日 23:51于 Maxime Ripard 写道： > >>> > >>> Hi Andre, > >>> > >>> On

Re: [linux-sunxi] Re: PoC tvin2jpeg_h264 with veisp scaling

Hi, > What i can suggest you to do is to make an experience, to check if the > hardware is been correctly configured for each task. > > Before selecting the subengine for each task change, to do a hardware > reset first. (In your tvin2jpeg.c, in function ve_selectsubengine put a > call to the

[linux-sunxi] Re: [PATCH v2 02/13] sunxi: Add initial support for R40

On Mon, Mar 06, 2017 at 04:05:07PM +0800, Chen-Yu Tsai wrote: > The R40 is the successor to the A20. It is a hybrid of the A20, A33 > and the H3. > > The R40's PIO controller is compatible with the A20, > Reuse the A20 UART and I2C muxing code by adding the R40's macro. > > The display pipeline

[linux-sunxi] Re: [PATCH v2 01/13] sunxi: Split up long Kconfig lines

On Mon, Mar 06, 2017 at 04:05:06PM +0800, Chen-Yu Tsai wrote: > Currently we have some lines in board/sunxi/Kconfig that are very long. > These line either provide default values for a set of SoCs, or limit > some option to a subset of sunxi SoCs. > > Fortunately Kconfig makes it easy to split

[linux-sunxi] [PATCH v2 05/13] sunxi: Add mmc[1-3] pinmux settings for R40

The PIO is generally compatible with the A20, except that it routes the full 8 bits and eMMC reset pins for mmc2. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- board/sunxi/board.c | 17 +++-- 1 file changed, 15

[linux-sunxi] [PATCH v2 03/13] sunxi: Enable AXP221s in I2C mode with the R40 SoC

The R40 SoC uses the AXP221s in I2C mode to supply power. Some regulator's common usages have changed, and also the recommended voltage for existing usages have changed. Update the defaults to match. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard

[linux-sunxi] [PATCH v2 12/13] sunxi: Add PSCI support for R40

The R40's CPU controls are a combination of sun6i and sun7i. All controls are in the CPUCFG block, and it seems the R40 does not have a PRCM block. The core reset, power gating and clamp controls are grouped like sun6i. Last, the R40 does not have a secure SRAM block. This patch adds a PSCI

[linux-sunxi] [PATCH v2 08/13] gpio: sunxi: Add compatible string for R40 PIO

The PIO on the R40 SoC is mostly compatible with the A20. Only a few pin functions for mmc2 were added to the PC pingroup, to support 8 bit eMMCs. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- drivers/gpio/sunxi_gpio.c | 1 + 1 file

[linux-sunxi] [PATCH v2 01/13] sunxi: Split up long Kconfig lines

Currently we have some lines in board/sunxi/Kconfig that are very long. These line either provide default values for a set of SoCs, or limit some option to a subset of sunxi SoCs. Fortunately Kconfig makes it easy to split them. The Kconfig language document states If multiple dependencies

[linux-sunxi] [PATCH v2 13/13] sunxi: Add support for Bananapi M2 Ultra

The Bananapi M2 Ultra is the first publicly available development board featuring the R40 SoC. This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra, as well as a defconfig for it. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard

[linux-sunxi] [PATCH v2 11/13] sunxi: Fix CPUCFG address for R40

The R40 has the CPUCFG block at the same address as the A20. Fix it. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

[linux-sunxi] [PATCH v2 04/13] sunxi: Fix watchdog reset function for R40

The watchdog found on the R40 SoC is the older variant found on the A20. Add the proper "#if defines" to make it work. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/include/asm/arch-sunxi/timer.h| 5 ++---

[linux-sunxi] [PATCH v2 00/13] sunxi: Add support for R40 SoC

Hi everyone, This is v2 of my Allwinner R40 SoC support series. Changes since v1: - Add Maxime's ack for all but the first patch. - Add a patch to split up very long Kconfig lines. This series adds support for the new R40 SoC. The R40 is marketed as the successor to the A20. It is mostly

[linux-sunxi] [PATCH v2 10/13] sunxi: Enable SPL for R40

Now that we can do DRAM initialization for the R40, we can enable SPL support for it. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- board/sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/sunxi/Kconfig

[linux-sunxi] [PATCH v2 06/13] sunxi: Set PLL lock enable bits for R40

According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has an extra "PLL lock control" register in the CCU, which controls whether the individual PLL lock status bits in each PLL's control register work or not. This patch enables it for all the PLLs. Signed-off-by: Chen-Yu Tsai

[linux-sunxi] [PATCH v2 02/13] sunxi: Add initial support for R40

The R40 is the successor to the A20. It is a hybrid of the A20, A33 and the H3. The R40's PIO controller is compatible with the A20, Reuse the A20 UART and I2C muxing code by adding the R40's macro. The display pipeline is the newer DE 2.0 variant. Block enabling video on R40 for now.