[linux-sunxi] Re: [PATCH v4 1/3] sunxi: add basic V3s support

11.03.2017, 10:09, "Icenowy Zheng" : > Basic U-Boot support is now present for V3s. > > Some memory addresses are changed specially for V3s, as the original > address map cannot fit into a so small DRAM. > > As the DRAM controller code needs a big refactor, the SPL support is >

[linux-sunxi] [PATCH 7/8] sunxi: add timing info for the DDR2 in V3s SoC

Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its timing param. Add the timing info for it, and make this chip selectable. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c |

[linux-sunxi] [PATCH 8/8] sunxi: add support for V3s DRAM controller

Allwinner V3s features a DRAM controller like the on in H3, but with a DDR2 DRAM. Add support for it. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 3 +++ board/sunxi/Kconfig | 9 - 2 files changed, 11 insertions(+), 1

[linux-sunxi] [PATCH 6/8] sunxi: add support for DDR2 DRAM for DesignWare-like DRAM controller

The DesignWare-like DRAM controllers in Allwinner chips have DDR2 DRAM support, add support for it in the driver. No real DDR2 chip info is added in this commit. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 ++ board/sunxi/Kconfig |

[linux-sunxi] [PATCH 5/8] sunxi: Add selective DRAM type and timing

DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng --- arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 30 ++

[linux-sunxi] [PATCH 3/8] sunxi: add option for 16-bit DW DRAM controller

Some Allwinner SoCs features a DesignWare-like controller with only 16 bit bus width. Add support for them. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 34 +- board/sunxi/Kconfig | 16

[linux-sunxi] [PATCH 4/8] sunxi: add bank detection code to H3 DRAM initialization code

Some DDR2 DRAM have only four banks, not eight. Add code to detect this situation. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c

[linux-sunxi] [PATCH 1/8] sunxi: makes an invisible option for H3-like DRAM controllers

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng

[linux-sunxi] [PATCH 2/8] sunxi: Rename bus-width related macros in H3 DRAM code

The DesignWare DRAM controller used by H3 and newer SoCs use a bit to identify whether the DRAM is half-width. As H3 itself come with 32-bit DRAM, the two modes of the bit used to be named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM they're really 8-bit and 16-bit. Rename

[linux-sunxi] [PATCH 0/8] Allwinner DesignWare DRAM controller refactors and V3s SPL support

Allwinner H5/A64/V3s/R40 SoCs all feature a DRAM controller like the one in Allwinner H3, which seems from DesignWare. They do not have properly licensed official DRAM initialization code (some have even no public readable code), but they can be supported by slightly altering the H3 code (this

[linux-sunxi] Re: [PATCH v2 07/11] iio: adc: sun4i-gpadc-iio: move code used in MFD probing to new function

Hi Icenowy, On 10/03/2017 20:36, Icenowy Zheng wrote: > > > 10.03.2017, 18:56, "Quentin Schulz" : >> This moves code used in MFD probing to a new sun4i_gpadc_probe_mfd >> function. >> >> Signed-off-by: Quentin Schulz >> ---