On 13/03/17 17:50, Icenowy Zheng wrote:
Hi Icenowy,
> Some Allwinner SoCs features a DesignWare-like controller with only 16
> bit bus width.
>
> Add support for them.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/mach-sunxi/dram_sunxi_dw.c | 34
On 13/03/17 17:50, Icenowy Zheng wrote:
> The DesignWare-like DRAM code used to set the controller defaultly to
> single rank mode, which makes it not able to detect the second rank.
>
> Set the default value to dual rank, thus the rank detection code can
> work and finally the rank setting will
On 15/03/17 00:26, André Przywara wrote:
> On 11/03/17 16:19, Icenowy Zheng wrote:
>> Some DDR2 DRAM have only four banks, not eight.
>>
>> Add code to detect this situation.
>>
>> Signed-off-by: Icenowy Zheng
> Reviewed-by: Andre Przywara
Argh, this
On 11/03/17 16:19, Icenowy Zheng wrote:
> DRAM chip varies, and one code cannot satisfy all DRAMs.
>
> Add options to select a timing set.
>
> Currently only DDR3-1333 (the original set) is added into it.
Yes, separating the timings sounds like a good idea. Eventually we
should move these
On 11/03/17 16:19, Icenowy Zheng wrote:
> Some DDR2 DRAM have only four banks, not eight.
>
> Add code to detect this situation.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Andre Przywara
Thanks,
Andre.
> ---
> arch/arm/mach-sunxi/dram_sunxi_dw.c
On 13/03/17 17:50, Icenowy Zheng wrote:
Hi Icenowy,
as mentioned before, I like this patch.
In general, can you rebase this series on top of sunxi/master? There are
some rather easy conflicts due to the H5 support being merged in.
One minor thing below...
> Allwinner SoCs after H3 (e.g. A64,
On 13/03/17 17:50, Icenowy Zheng wrote:
> The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
> identify whether the DRAM is half-width.
>
> As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
> named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with
On 13 March 2017 at 06:33, Simon Glass wrote:
> On 8 March 2017 at 16:34, Jernej Skrabec wrote:
>> Despite the comment in the code, CSC unit is never used. According to
>> the only public description of DW HDMI controller (i.MX6 manual), CSC
>> unit is
On 13 March 2017 at 06:33, Simon Glass wrote:
> On 8 March 2017 at 16:34, Jernej Skrabec wrote:
>> Function hdmi_lookup_n_cts() is feed with clock in Hz, which gets
>> compared with clocks in kHz. Fix that by converting all clocks to Hz.
>>
>>
Hi,
Dne 14.3.2017 v 07:53 Jernej Škrabec napsal(a):
> Hi,
>
> Dne ponedeljek, 13. marec 2017 ob 13:33:43 CET je Simon Glass napisal(a):
>> Hi,
>>
>> On 8 March 2017 at 16:34, Jernej Skrabec wrote:
>>> This is needed for HDMI, which will be added later.
>>>
>>>
On Tue, Feb 28, 2017 at 8:08 PM, Icenowy Zheng wrote:
> Allwinner pin controllers are also GPIO controllers.
>
> Currently, if GPIOLIB is forgot to be chosen, the build of
> pinctrl-sunxi.c will fail for lacking a lot of gpiochip_* functions.
>
> Select GPIOLIB to ensure this
Hi Jonathan,
On 14/03/2017 06:18, Icenowy Zheng wrote:
>
>
> 14.03.2017, 05:08, "Jonathan Cameron" :
>> On 10/03/17 10:39, Quentin Schulz wrote:
>>> This adds support for the Allwinner A33 thermal sensor.
>>>
>>> Unlike the A10, A13 and A31, the Allwinner A33 only has one
Hi,
Dne ponedeljek, 13. marec 2017 ob 13:33:43 CET je Simon Glass napisal(a):
> Hi,
>
> On 8 March 2017 at 16:34, Jernej Skrabec wrote:
> > This is needed for HDMI, which will be added later.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
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