ok I will thanks :)
On Friday, March 24, 2017 at 10:24:36 PM UTC+2, Icenowy Zheng wrote:
>
>
> 2017年3月25日 上午3:07于 Eyad Majali 写道:
> >
> > Hi
> > I followed Icenowy Zheng's patches to enable sun8iw3 thermal sensor , it
> compiles OK , but when enabling clk-a31-pll2 the kernel
2017年3月25日 上午3:07于 Eyad Majali 写道:
>
> Hi
> I followed Icenowy Zheng's patches to enable sun8iw3 thermal sensor , it compiles OK , but when enabling clk-a31-pll2 the kernel hangs and doesnt boot , any help how to fix that ??
Please wait for Quentin Schulz's new thermal
Hi
I followed Icenowy Zheng's patches to enable sun8iw3 thermal sensor , it
compiles OK , but when enabling clk-a31-pll2 the kernel hangs and doesnt
boot , any help how to fix that ??
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I fixed the problem by modifying drivers/pwm/core.c as following:
in function pwmchip_add_with_polarity
for (i = 0; i < chip->npwm; i++) {
pwm = >pwms[i];
pwm->chip = chip;
pwm->pwm = chip->base + i;
pwm->hwpwm = i;
pwm->state.polarity = polarity;
Dne petek, 24. marec 2017 ob 16:53:07 CET je Maxime Ripard napisal(a):
> On Wed, Mar 22, 2017 at 06:19:12PM +0100, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne sreda, 22. marec 2017 ob 08:45:48 CET je Maxime Ripard napisal(a):
> > > On Tue, Mar 21, 2017 at 11:26:46PM +0100, Jernej Škrabec wrote:
> >
On Thu, Mar 23, 2017 at 03:34:18AM +0800, Icenowy Zheng wrote:
>
> 2017年3月23日 03:24于 Maxime Ripard 写道:
> >
> > On Fri, Mar 17, 2017 at 11:43:43PM +0800, Icenowy Zheng wrote:
> > > Lichee Pi Zero features a dock, which adds some functions, and should be
> > >
On Wed, Mar 22, 2017 at 06:19:12PM +0100, Jernej Škrabec wrote:
> Hi,
>
> Dne sreda, 22. marec 2017 ob 08:45:48 CET je Maxime Ripard napisal(a):
> > On Tue, Mar 21, 2017 at 11:26:46PM +0100, Jernej Škrabec wrote:
> > > Hi,
> > >
> > > Dne torek, 21. marec 2017 ob 20:34:33 CET je Maxime Ripard
Hi,
On Thu, Mar 23, 2017 at 10:24:44PM +0100, Jelle van der Waa wrote:
> Enable the WiFi (AP6212) chip and eMMC support for the NanoPi NEO Air.
>
> Signed-off-by: Jelle van der Waa
> ---
> arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts | 45
> +++
> 1
Following LVDS features might be supported (according to BSP), but are
unimplemented due to lack of proper hardware:
- dual channel LVDS
- choosing between NS or JEIDA mode
- cross-polarity support
Add at least some comments about them.
Signed-off-by: Priit Laes
---
sunxi_rgb2yuv_coef is readonly and never modified.
Signed-off-by: Priit Laes
---
drivers/video/sunxi_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index bcd33dd..a12c4c3 100644
---
In commit 2beaa601c849 ("clk: sunxi-ng: Implement minimum for
multipliers"), the multiplier minimums in the set_rate callback
for NM and NKMP style clocks were not updated.
This patch fixes them to match their round_rate callbacks.
Fixes: 2beaa601c849 ("clk: sunxi-ng: Implement minimum for
A zero multiplier does not make sense for clocks.
Use 1 as the minimum when a multiplier minimum isn't specified.
Fixes: 2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_nk.c | 8
Hi Maxime,
Here's a few fixes I came up with while thinking more about how to
implement some of the tricky clocks on the A83T.
Please have a look. The first 2 might need to go in stable, but I'll
leave the decision to you.
Regards
ChenYu
Chen-Yu Tsai (3):
clk: sunxi-ng: use 1 as fallback
On Fri, Mar 24, 2017 at 3:55 PM, Quentin Schulz
wrote:
> Hi,
>
> On 23/03/2017 10:52, Chen-Yu Tsai wrote:
>> On Thu, Mar 23, 2017 at 5:35 PM, Sebastian Reichel wrote:
>>> Hi,
>>>
>>> On Wed, Mar 22, 2017 at 12:34:45PM +0800, Chen-Yu Tsai wrote:
Hi,
On 23/03/2017 10:52, Chen-Yu Tsai wrote:
> On Thu, Mar 23, 2017 at 5:35 PM, Sebastian Reichel wrote:
>> Hi,
>>
>> On Wed, Mar 22, 2017 at 12:34:45PM +0800, Chen-Yu Tsai wrote:
>>> P.S. I'm thinking about having MFD_AXP20X imply its various sub-drivers.
>>> Not sure if that
24.03.2017, 15:46, "Ulf Hansson" :
> On 16 March 2017 at 14:29, Icenowy Zheng wrote:
>> The controller's errors are usually normal (for example, for MMC or SDIO
>> cards, some errors are expected to happen; and for boards without a
>> dedicated card
24.03.2017, 14:56, "Chen-Yu Tsai" :
> On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng wrote:
>> 24.03.2017, 11:05, "Chen-Yu Tsai" :
>>> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
The config structure of H3 in
On 16 March 2017 at 14:29, Icenowy Zheng wrote:
> The controller's errors are usually normal (for example, for MMC or SDIO
> cards, some errors are expected to happen; and for boards without a
> dedicated card detect pin the error info will even flood console and
> hide other
On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng wrote:
>
>
> 24.03.2017, 11:05, "Chen-Yu Tsai" :
>> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
>>> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>>> register
24.03.2017, 11:05, "Chen-Yu Tsai" :
> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
>> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>> register offset missing.
>>
>> Add it. Because it's a SoC after A33, its PHYCTL offset should
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