于 2017年5月10日 GMT+08:00 上午7:44:21, "André Przywara" 写到:
>On 26/04/17 15:50, Icenowy Zheng wrote:
>> From: Icenowy Zheng
>>
>> As we added LPDDR3 support in the former patch, we need a set of
>timing
>> info to really enable it.
>>
>> Add the timing info used by stock boot0.
>
>When I checked t
On 26/04/17 15:50, Icenowy Zheng wrote:
> From: Icenowy Zheng
>
> As we added LPDDR3 support in the former patch, we need a set of timing
> info to really enable it.
>
> Add the timing info used by stock boot0.
When I checked the disassembly/decompile for the Pine64 libdram, I found
some more r
On 26/04/17 15:50, Icenowy Zheng wrote:
> From: Icenowy Zheng
>
> DRAM chip varies, and one code cannot satisfy all DRAMs.
>
> Add options to select a timing set.
>
> Currently only DDR3-1333 (the original set) is added into it.
Confirmed that this just moves the code, no changes in the actual
On Fri, May 05, 2017 at 08:39:31PM +0800, Icenowy Zheng wrote:
> >> > > + /* Set base coordinates */
> >> > > + DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
> >> > > + state->crtc_x, state->crtc_y);
> >> > > + regmap_write(mixer->engine.regs,
> >> > > +
1;4601;0c
On Fri, May 05, 2017 at 08:34:16PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月5日 GMT+08:00 下午8:30:35, Maxime Ripard
> 写到:
> >On Fri, May 05, 2017 at 04:53:43PM +0800, icen...@aosc.io wrote:
> >> > > + de2_clocks: clock@100 {
> >> > > + compatibl
Hi everyone,
I think we still need to discuss on a thermal sensor driver on some
Allwinner SoCs (specially, H3/A64/H5/A83T/R40).
These SoCs seem to have already a stable design of thermal sensor,
which can easily add or remove several thermal channels (H3 has
only one thermal channel, H5 2, other