[linux-sunxi] [PATCH] pinctrl: sunxi: rename R_PIO i2c pin function name

The I2C pin functions in R_PIO used to be named "s_twi". As we usually use the name "i2c" instead of "twi" in the mainline kernel, change these names to "s_i2c" for consistency. The "s_twi" functions are not yet referenced by any device trees in mainline kernel so I think it's safe to change the

[linux-sunxi] Re: [PATCH v3 0/2] Last step to working Allwinner R40 pinctrl

在 2017-07-22 10:50，Icenowy Zheng 写道： This patchset contains only two patches. The first one is a minor fix for the A10 pinctrl driver, add a function of a pin, which used to be missing in A10/A20 pinctrl driver. Thanks for Chen-Yu for discovering it when reviewing my R40 pinctrl patchset.

[linux-sunxi] Help needed: FEL and UMS support in A64 U-boot

Dear List: I have added a 16GB eMMC chip to my OrangePi Win Plus, with the intention of not having it hogging one of my microSD cards. (I may be one of the weird people that likes to hack hardware as well as software.) Now I need some help to put the actual system image into the eMMC. I have

[linux-sunxi] [PATCH] net-next: stmmac: dwmac-sun8i: fix of_table.cocci warnings

ng Wu <fengguang...@intel.com> --- url: https://github.com/0day-ci/linux/commits/Corentin-Labbe/dt-bindings-net-add-compatible-for-internal-sun8i-h3-sun8i-v3s-PHYs/20170729-174950 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next dwmac-sun8i.c |1 + 1 fil

[linux-sunxi] [PATCH v3 04/12] ASoC: sun4i-i2s: Add TX FIFO offset to quirks

From: Marcus Cooper It has been seen that the newer SoCs have a different TX FIFO address. Add this to the quirks structure. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-)

[linux-sunxi] [PATCH v3 11/12] ASoC: sun4i-i2s: Update global enable with bitmask

From: Marcus Cooper The default value of the config register is different on newer SoCs and therefore enabling/disabling with a register write will clear bits used to set the direction of the clock and frame pins. Signed-off-by: Marcus Cooper ---

[linux-sunxi] [PATCH v3 01/12] ASoC: sun4i-i2s: Extend quirks scope

From: Marcus Cooper In preparation for the changes required to support newer SoCs then quirks has been moved and also added to the device structure. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 22 ++ 1 file

[linux-sunxi] [PATCH v3 00/12] ASoC: Add I2S support for Allwinner H3 SoCs

From: Marcus Cooper Hi All, please find attached a series of patches to bring i2s support to the Allwinner H3 SoC. This has been tested with the following setups: A20 Olimex EVB connected to a pcm5102 Orange Pi 2 connected to a uda1380 Orange Pi 2 hdmi audio playback Pine

[linux-sunxi] [PATCH v3 07/12] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup

From: Marcus Cooper On newer SoCs the bit fields for the blck and lrclk polarity are in a different locations. Use regmap fields to set the polarity bits as intended. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 45

[linux-sunxi] [PATCH v3 08/12] ASoC: sun4i-i2s: Add mclk enable regmap field

From: Marcus Cooper The location of the mclk output enable bit is different on newer SoCs. Use a regmap field to enable it. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 22 +++--- 1 file changed, 19 insertions(+), 3

[linux-sunxi] [PATCH v3 05/12] ASoC: sun4i-i2s: Add regmap fields for channels

From: Marcus Cooper On the original i2s block the channel mapping and selection were configured for stereo audio by default: This is not the case with the newer SoCs and they are also located at different offsets. To support the newer SoC then regmap fields have been added

[linux-sunxi] [PATCH v3 10/12] ASoC: sun4i-i2s: Check for slave select bit

From: Marcus Cooper The newer SoCs do not have this setting. Instead they set the pin direction. Add a check to see if the bit is valid and if so set it accordingly. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 38

[linux-sunxi] [PATCH v3 06/12] ASoC: sun4i-i2s: Add changes for wss and sr

From: Marcus Cooper On newer SoCs the location of the slot width select and sample resolution are different and also there is a bigger range of support. For the current supported rates then an offset is required. Signed-off-by: Marcus Cooper ---

[linux-sunxi] [PATCH v3 09/12] ASoC: sun4i-i2s: Add regmap field to set format

From: Marcus Cooper On the newer SoCs the bits to configure the operational mode are located in a different register. Add a regmap field so that this location can be configured. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 15

[linux-sunxi] [PATCH v3 12/12] ASoC: sun4i-i2s: Add support for H3

From: Marcus Cooper The sun8i-h3 introduces a lot of changes to the i2s block such as different register locations, extended clock division and more operational modes. As we have to consider the earlier implementation then these changes need to be isolated. Signed-off-by:

[linux-sunxi] [PATCH v3 02/12] ASoC: sun4i-i2s: Add clkdiv offsets to quirks

From: Marcus Cooper The BCLKDIV and MCLKDIV found on newer SoCs start from an offset of 1. Add the functionality to adjust the division values according to the needs to the device being used. Signed-off-by: Marcus Cooper ---

[linux-sunxi] [PATCH v3 03/12] ASoC: sun4i-i2s: Add regmap config to quirks

From: Marcus Cooper The newer SoCs have a larger range than the original SoC that this driver was developed for. By adding the regmap config to the quirks then the driver can initialise the managed register map correctly. Signed-off-by: Marcus Cooper

[linux-sunxi] Re: [PATCH 0/3] net-next: stmmac: support future possible different internal phy mode

On Fri, Jul 28, 2017 at 10:54:30AM -0700, Florian Fainelli wrote: > On 07/28/2017 07:44 AM, Corentin Labbe wrote: > > On Fri, Jul 28, 2017 at 04:36:00PM +0200, Andrew Lunn wrote: > I've probably asked this before: Does the internal PHY use a different > PHY ID in registers 2 and 3? >