[linux-sunxi] [PATCH 1/2] dt-bindings: add compatible string for Allwinner V3s SoC

The compatible string for Allwinner V3s SoC used to be missing. Add it to the binding document. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file changed, 1 insertion(+)

[linux-sunxi] [PATCH 2/2] ARM: sunxi: add support for R40 SoC

Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng --- Documentation/arm/sunxi/README | 6 ++ Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch/arm/mach-sunxi/sunxi.c

[linux-sunxi] Re: [PATCH] ARM: sun8i: a83t: Add device tree for Sinovoip Bananapi BPI-M3

Hi Chen-Yu, [auto build test ERROR on robh/for-next] [also build test ERROR on v4.13-rc5 next-20170817] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [linux-sunxi] [PATCH v5 5/8] ASoC: sun4i-i2s: Add regmap field to set DAI format

On Sat, Aug 19, 2017 at 8:48 PM, wrote: > From: Marcus Cooper > > On the newer SoCs the bits to configure the operational mode are > located in a different register. Add a regmap field so that this > location can be configured. > > Signed-off-by:

Re: [linux-sunxi] [PATCH v5 4/8] ASoC: sun4i-i2s: Add mclk enable regmap field

On Sat, Aug 19, 2017 at 8:48 PM, wrote: > From: Marcus Cooper > > The location of the mclk output enable bit is different on newer > SoCs. Use a regmap field to enable it. > > Signed-off-by: Marcus Cooper Reviewed-by: Chen-Yu

Re: [linux-sunxi] [PATCH v5 1/8] ASoC: sun4i-i2s: Add regmap fields for channels

On Sat, Aug 19, 2017 at 8:48 PM, wrote: > From: Marcus Cooper > > On the original i2s block the channel mapping and selection were > configured for stereo audio by default: This is not the case with > the newer SoCs and they are also located at

Re: [linux-sunxi] [PATCH v5 3/8] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup

On Sat, Aug 19, 2017 at 8:48 PM, wrote: > From: Marcus Cooper > > On newer SoCs the bit fields for the blck and lrclk polarity are in > a different locations. Use regmap fields to set the polarity bits > as intended. > > Signed-off-by: Marcus Cooper

[linux-sunxi] [PATCH v5 5/8] ASoC: sun4i-i2s: Add regmap field to set DAI format

From: Marcus Cooper On the newer SoCs the bits to configure the operational mode are located in a different register. Add a regmap field so that this location can be configured. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 15

[linux-sunxi] [PATCH v5 4/8] ASoC: sun4i-i2s: Add mclk enable regmap field

From: Marcus Cooper The location of the mclk output enable bit is different on newer SoCs. Use a regmap field to enable it. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 16 ++-- 1 file changed, 14 insertions(+), 2

[linux-sunxi] [PATCH v5 6/8] ASoC: sun4i-i2s: Check for slave select bit

From: Marcus Cooper The newer SoCs do not have this setting. Instead they set the pin direction. Add a check to see if the bit is valid and if so set it accordingly. Signed-off-by: Marcus Cooper Reviewed-by: Chen-Yu Tsai ---

[linux-sunxi] [PATCH v5 3/8] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup

From: Marcus Cooper On newer SoCs the bit fields for the blck and lrclk polarity are in a different locations. Use regmap fields to set the polarity bits as intended. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 45

[linux-sunxi] [PATCH v5 7/8] ASoC: sun4i-i2s: Update global enable with bitmask

From: Marcus Cooper The default value of the config register is different on newer SoCs and therefore enabling/disabling with a register write will clear bits used to set the direction of the clock and frame pins. Signed-off-by: Marcus Cooper

[linux-sunxi] [PATCH v5 2/8] ASoC: sun4i-i2s: Add regfields for word size select and sample resolution

From: Marcus Cooper On newer SoCs the location of the slot width select and sample resolution are different and also there is a bigger range of support. For the current supported rates then an offset is required. Signed-off-by: Marcus Cooper

[linux-sunxi] [PATCH v5 8/8] ASoC: sun4i-i2s: Add support for H3

From: Marcus Cooper The sun8i-h3 introduces a lot of changes to the i2s block such as different register locations, extended clock division and more operational modes. As we have to consider the earlier implementation then these changes need to be isolated. None of the new

[linux-sunxi] [PATCH v5 0/8] ASoC: Add I2S support for Allwinner H3 SoCs

From: Marcus Cooper Hi All, please find attached a series of patches to bring i2s support to the Allwinner H3 SoC. This has been tested with the following setups: A20 Olimex EVB connected to a pcm5102 Orange Pi 2 connected to a uda1380 Orange Pi 2 hdmi audio playback Pine

[linux-sunxi] [PATCH v5 1/8] ASoC: sun4i-i2s: Add regmap fields for channels

From: Marcus Cooper On the original i2s block the channel mapping and selection were configured for stereo audio by default: This is not the case with the newer SoCs and they are also located at different offsets. To support the newer SoC then regmap fields have been added

Re: [linux-sunxi] Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

在 2017-08-19 17:11，Chen-Yu Tsai 写道： On Tue, Aug 15, 2017 at 4:52 PM, wrote: 在 2017-08-15 13:55，Icenowy Zheng 写道： Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by:

Re: [linux-sunxi] Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

On Tue, Aug 15, 2017 at 4:52 PM, wrote: > 在 2017-08-15 13:55，Icenowy Zheng 写道： >> >> Allwinner R40 SoC have a clock controller module in the style of the >> SoCs beyond sun6i, however, it's more rich and complex. >> >> Add support for it. >> >> Signed-off-by: Icenowy Zheng