So far we used the separate mksunxiboot tool for generating a bootable
image for Allwinner SPLs, probably just for historical reasons.
Use the mkimage framework to generate a so called eGON image the
Allwinner BROM expects.
The new image type is called "sunxi_egon", to differentiate it
from the
Switch the SPL boot image generation from using mksunxiboot to the new
sunxi_egon format of mkimage.
Verified to create identical results for all 144 Allwinner boards.
Signed-off-by: Andre Przywara
---
scripts/Makefile.spl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
On Sat, Dec 22, 2018 at 12:48 AM Chen-Yu Tsai wrote:
>
> On Fri, Dec 21, 2018 at 11:21 PM wrote:
> >
> > From: Marcus Cooper
> >
> > Extend the functionality of the driver to include support of 20 and
> > 24 bits per sample for the earlier SoCs.
> >
> > Newer SoCs can also handle 32bit samples.
On Fri, Dec 21, 2018 at 11:21 PM wrote:
>
> From: Marcus Cooper
>
> On the newer SoCs this is set by default to transfer a 0 after
> each sample in each slot. Add the regmap field to configure this
> and set it so that it pads the sample with 0s.
>
> Signed-off-by: Marcus Cooper
The code
From: Ondrej Jirman
When cedrus_hw_probe is called, v4l2_dev is not yet initialized.
Use dev_err instead.
Signed-off-by: Ondrej Jirman
---
.../staging/media/sunxi/cedrus/cedrus_hw.c| 28 +--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git
On Fri, Dec 21, 2018 at 11:21 PM wrote:
>
> From: Marcus Cooper
>
> Also add offset to RX channel select
>
> Signed-off-by: Marcus Cooper
Commit log seems a bit lacking. You could probably explain how you
found this, either when comparing datasheet macros, or some actual
error manifested and
On Fri, Dec 21, 2018 at 11:21 PM wrote:
>
> From: Marcus Cooper
>
> Extend the functionality of the driver to include support of 20 and
> 24 bits per sample for the earlier SoCs.
>
> Newer SoCs can also handle 32bit samples.
>
> Signed-off-by: Marcus Cooper
> ---
> sound/soc/sunxi/sun4i-i2s.c
On Fri, Dec 21, 2018 at 11:21 PM wrote:
>
> From: Marcus Cooper
>
> Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
> to reflect this.
>
> Signed-off-by: Marcus Cooper
> ---
> sound/soc/sunxi/sun4i-i2s.c | 29 +
> 1 file changed, 9
From: Marcus Cooper
The clock division circuitry is different on the H3 and later SoCs.
The division of bclk is now based on pll2.
Signed-off-by: Marcus Cooper
---
sound/soc/sunxi/sun4i-i2s.c | 82 +
1 file changed, 56 insertions(+), 26 deletions(-)
diff
From: Marcus Cooper
There is no need to set the clock and calculate the division of
the audio pll for the bclk and sync signals when they are not
required.
Signed-off-by: Marcus Cooper
---
sound/soc/sunxi/sun4i-i2s.c | 144 +++-
1 file changed, 77
From: Marcus Cooper
On the newer SoCs this is set by default to transfer a 0 after
each sample in each slot. Add the regmap field to configure this
and set it so that it pads the sample with 0s.
Signed-off-by: Marcus Cooper
---
sound/soc/sunxi/sun4i-i2s.c | 15 +++
1 file changed,
From: Marcus Cooper
Extend the functionality of the driver to include support of 20 and
24 bits per sample for the earlier SoCs.
Newer SoCs can also handle 32bit samples.
Signed-off-by: Marcus Cooper
---
sound/soc/sunxi/sun4i-i2s.c | 41 ++---
1 file changed,
From: Marcus Cooper
Also add offset to RX channel select
Signed-off-by: Marcus Cooper
---
sound/soc/sunxi/sun4i-i2s.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index adb988ae9ac5..93a484d7e228 100644
---
From: Marcus Cooper
The i2s block supports multi-lane i2s output however this functionality
is only possible in earlier SoCs where the pins are exposed and for
the i2s block used for HDMI audio on the later SoCs.
To enable this functionality, an optional property has been added to
the bindings.
From: Marcus Cooper
Some codecs require a different amount of a bit clocks per frame than
what is calculated by the sample width. Use the tdm slot bindings to
provide this mechanism.
Signed-off-by: Marcus Cooper
---
sound/soc/sunxi/sun4i-i2s.c | 22 --
1 file changed, 20
From: Marcus Cooper
The i2s block can be used to pass PCM data over multiple channels
and is sometimes used for the audio side of an HDMI connection.
Signed-off-by: Marcus Cooper
---
sound/soc/sunxi/sun4i-i2s.c | 121 +++-
1 file changed, 64 insertions(+), 57
From: Marcus Cooper
Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
to reflect this.
Signed-off-by: Marcus Cooper
---
sound/soc/sunxi/sun4i-i2s.c | 29 +
1 file changed, 9 insertions(+), 20 deletions(-)
diff --git
From: Marcus Cooper
Hi All,
here is a patch series to add some improvements to the sun4i-i2s driver
found whilst getting slave clocking and hdmi audio working on the newer
SoCs. Since the last push there has been some activity getting surround
sound working and this is included.
The
On Thu, Dec 20, 2018 at 06:24:34PM +0530, Jagan Teki wrote:
> Unfortunately default CSI_SCLK rate cannot work properly to
> drive the connected sensor interface, particularly on few
> Allwinner SoC's like A64.
>
> So, add mod_rate quirk via driver data so-that the respective
> SoC's which require
On Fri, 21 Dec 2018, Priit Laes wrote:
> On Fri, Dec 21, 2018 at 09:26:58AM +, Lee Jones wrote:
> > On Fri, 21 Dec 2018, Priit Laes wrote:
> >
> > > On Fri, Dec 21, 2018 at 08:39:27AM +, Lee Jones wrote:
> > > > On Tue, 11 Dec 2018, Priit Laes wrote:
> > > >
> > > > > From: Olliver
On Fri, Dec 21, 2018 at 09:26:58AM +, Lee Jones wrote:
> On Fri, 21 Dec 2018, Priit Laes wrote:
>
> > On Fri, Dec 21, 2018 at 08:39:27AM +, Lee Jones wrote:
> > > On Tue, 11 Dec 2018, Priit Laes wrote:
> > >
> > > > From: Olliver Schinagl
> > > >
> > > > The current axp20x names the
On Fri, 21 Dec 2018, Priit Laes wrote:
> On Fri, Dec 21, 2018 at 08:39:27AM +, Lee Jones wrote:
> > On Tue, 11 Dec 2018, Priit Laes wrote:
> >
> > > From: Olliver Schinagl
> > >
> > > The current axp20x names the ramping register 'scal' which probably
> > > means scaling. Since the
On Fri, Dec 21, 2018 at 08:39:27AM +, Lee Jones wrote:
> On Tue, 11 Dec 2018, Priit Laes wrote:
>
> > From: Olliver Schinagl
> >
> > The current axp20x names the ramping register 'scal' which probably
> > means scaling. Since the register really has nothing to do with
> > scaling, but
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