On 06/01/2019 19:22, Jagan Teki wrote:
> On Sun, Jan 6, 2019 at 6:49 PM André Przywara wrote:
>>
>> On 31/12/2018 16:59, Jagan Teki wrote:
>>
>> Hi Jagan,
>>
>> many thanks for picking this up, I was about to come back to this
>> myself. I am looking at the pinctrl part at the moment, so good you
On 31/12/2018 16:59, Jagan Teki wrote:
> Clock control unit comprises of parent clocks, gates, multiplexers,
> dividers, multipliers, pre/post dividers and flags etc.
>
> So, the U-Boot implementation of ccu has divided into gates and tree.
> gates are generic clock configuration of enable/disable
On 1/6/19 8:33 PM, Jagan Teki wrote:
> Now clock and reset drivers are available for respective
> SoC's so use clk and reset ops on musb driver.
>
> Signed-off-by: Jagan Teki
> Acked-by: Maxime Ripard
Reviewed-by: Marek Vasut
--
Best regards,
Marek Vasut
--
You received this message because
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on musb driver.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
Changes for v5.1:
- use dev_err instead of pr_err
drivers/usb/musb-new/sunxi.c | 79 ++--
1 file changed
On Sun, Jan 6, 2019 at 6:49 PM André Przywara wrote:
>
> On 31/12/2018 16:59, Jagan Teki wrote:
>
> Hi Jagan,
>
> many thanks for picking this up, I was about to come back to this
> myself. I am looking at the pinctrl part at the moment, so good you are
> working on the clocks!
>
> TL;DR: I am goo
On Mon, Dec 24, 2018 at 8:57 PM Jagan Teki wrote:
>
> On Fri, Dec 21, 2018 at 6:30 PM Maxime Ripard
> wrote:
> >
> > On Thu, Dec 20, 2018 at 06:24:34PM +0530, Jagan Teki wrote:
> > > Unfortunately default CSI_SCLK rate cannot work properly to
> > > drive the connected sensor interface, particula
On Fri, Dec 21, 2018 at 2:26 AM Jagan Teki wrote:
>
> On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
> wrote:
> >
> > On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > > Video start delay can be computed by subtracting total vertical
> > > timing with front porch timing and with add
On 31/12/2018 16:59, Jagan Teki wrote:
Hi Jagan,
many thanks for picking this up, I was about to come back to this
myself. I am looking at the pinctrl part at the moment, so good you are
working on the clocks!
TL;DR: I am good with the first patches, but would like to drop the last
five 5 patche
On Mon, Dec 31, 2018 at 10:30 PM Jagan Teki wrote:
>
> Although the previous version[1] is properly handled the clock gates
> with enable and disable management, but this series is trying to add
> some more complex Allwinner CLK architecture by handling parent clock
> and other CLK attributes.
>
>
