On Thu, Jan 03, 2019 at 05:03:13PM +0100, Zoltan HERPAI wrote:
> Hi Jagan, Adam,
>
> On Thu, 3 Jan 2019, Jagan Teki wrote:
>
> > On Thu, Jan 3, 2019 at 6:57 PM Zoltan HERPAI wrote:
> > >
> > > Hi all,
> > >
> > > The DTS resync between 2018.09 and 2018.11 seems to have broken the MMC
> > >
On Mon, Jan 07, 2019 at 02:09:12PM +, Andre Przywara wrote:
> > > What is MISC, exactly? Seems like an artefact clock to me, some
> > > placeholder you need because gate clocks are handled separately in
> > > the gates struct. Should this be called something with SIMPLE
> > > instead, or GATE?
On Mon, Jan 7, 2019 at 7:42 PM Maxime Ripard wrote:
>
> On Fri, Dec 21, 2018 at 02:26:11AM +0530, Jagan Teki wrote:
> > On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
> > wrote:
> > >
> > > On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > > > Video start delay can be computed by
On Fri, Dec 21, 2018 at 02:26:11AM +0530, Jagan Teki wrote:
> On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
> wrote:
> >
> > On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > > Video start delay can be computed by subtracting total vertical
> > > timing with front porch timing and
On Mon, 7 Jan 2019 14:01:01 +0100
Maxime Ripard wrote:
Hi,
> On Mon, Jan 07, 2019 at 01:03:33AM +, André Przywara wrote:
> > On 31/12/2018 16:59, Jagan Teki wrote:
> > > Clock control unit comprises of parent clocks, gates,
> > > multiplexers, dividers, multipliers, pre/post dividers and
On Mon, Dec 24, 2018 at 08:57:48PM +0530, Jagan Teki wrote:
> On Fri, Dec 21, 2018 at 6:30 PM Maxime Ripard
> wrote:
> >
> > On Thu, Dec 20, 2018 at 06:24:34PM +0530, Jagan Teki wrote:
> > > Unfortunately default CSI_SCLK rate cannot work properly to
> > > drive the connected sensor interface,
On Mon, Dec 31, 2018 at 10:29:27PM +0530, Jagan Teki wrote:
> Sopine has Winbond SPI flash, so enable the same to use
> flash on Sopine board.
>
> Cc: TL Lim
> Signed-off-by: Jagan Teki
> ---
> .../dts/sun50i-a64-sopine-baseboard-u-boot.dtsi | 16
>
On Mon, Jan 07, 2019 at 01:03:33AM +, André Przywara wrote:
> On 31/12/2018 16:59, Jagan Teki wrote:
> > Clock control unit comprises of parent clocks, gates, multiplexers,
> > dividers, multipliers, pre/post dividers and flags etc.
> >
> > So, the U-Boot implementation of ccu has divided
Hi,
On Mon, 2019-01-07 at 11:49 +0800, Randy Li wrote:
> On 12/12/18 8:51 PM, Paul Kocialkowski wrote:
> > Hi,
> >
> > On Wed, 2018-12-05 at 21:59 +0100, Jernej Škrabec wrote:
> >
> > > > +
> > > > +#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE 0x01
> > > > +#define
