[linux-sunxi] [PATCH 2/6] media: cedrus: Add a quirk for not setting DMA offset
H6 VPU doesn't work if DMA offset is set.
Add a quirk for it.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus.h| 3 +++
drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h
b/drivers/staging/media/sunxi/cedrus/cedrus.h
index 4aedd24a9848..c57c04b41d2e 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
@@ -28,6 +28,8 @@
#define CEDRUS_CAPABILITY_UNTILED BIT(0)
+#define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0)
+
enum cedrus_codec {
CEDRUS_CODEC_MPEG2,
@@ -91,6 +93,7 @@ struct cedrus_dec_ops {
struct cedrus_variant {
unsigned intcapabilities;
+ unsigned intquirks;
};
struct cedrus_dev {
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
index 0acf219a8c91..fbfff7c1c771 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
@@ -177,7 +177,8 @@ int cedrus_hw_probe(struct cedrus_dev *dev)
*/
#ifdef PHYS_PFN_OFFSET
- dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET;
+ if (!(variant->quirks & CEDRUS_QUIRK_NO_DMA_OFFSET))
+ dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET;
#endif
ret = of_reserved_mem_device_init(dev->dev);
--
2.20.1
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[linux-sunxi] [PATCH 4/6] dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1
This introduces a new compatible for the H6 SRAM C1 section, that is compatible with the SRAM C1 section as found on the A10. Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt index ab5a70bb9a64..380246a805f2 100644 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt @@ -63,6 +63,7 @@ The valid sections compatible for H5 are: The valid sections compatible for H6 are: - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c +- allwinner,sun50i-h6-sram-c1, allwinner,sun4i-a10-sram-c1 The valid sections compatible for F1C100s are: - allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d -- 2.20.1 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 5/6] arm64: dts: allwinner: h6: Add support for the SRAM C1 section
Add a node for H6 SRAM C1 section.
Manual calls it VE SRAM, but for consistency with older SoCs, SRAM C1
name is used.
Signed-off-by: Jernej Skrabec
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index d93a7add67e7..247dc0a5ce89 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -167,6 +167,20 @@
reg = <0x 0x1e000>;
};
};
+
+ sram_c1: sram@1a0 {
+ compatible = "mmio-sram";
+ reg = <0x01a0 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01a0 0x20>;
+
+ ve_sram: sram-section@0 {
+ compatible =
"allwinner,sun50i-h6-sram-c1",
+
"allwinner,sun4i-a10-sram-c1";
+ reg = <0x00 0x20>;
+ };
+ };
};
ccu: clock@3001000 {
--
2.20.1
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[linux-sunxi] [PATCH 1/6] dt-bindings: media: cedrus: Add H6 compatible
This adds a compatible for H6. H6 VPU supports 10-bit HEVC decoding and additional AFBC output format for HEVC. Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/media/cedrus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt index bce0705df953..20c82fb0c343 100644 --- a/Documentation/devicetree/bindings/media/cedrus.txt +++ b/Documentation/devicetree/bindings/media/cedrus.txt @@ -13,6 +13,7 @@ Required properties: - "allwinner,sun8i-h3-video-engine" - "allwinner,sun50i-a64-video-engine" - "allwinner,sun50i-h5-video-engine" + - "allwinner,sun50i-h6-video-engine" - reg : register base and length of VE; - clocks : list of clock specifiers, corresponding to entries in the clock-names property; -- 2.20.1 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 6/6] arm64: dts: allwinner: h6: Add Video Engine node
This adds the Video engine node for H6. It can use whole DRAM range so
there is no need for reserved memory node.
Signed-off-by: Jernej Skrabec
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 247dc0a5ce89..de4b7a1f1012 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -146,6 +146,17 @@
};
};
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun50i-h6-video-engine";
+ reg = <0x01c0e000 0x2000>;
+ clocks = < CLK_BUS_VE>, < CLK_VE>,
+< CLK_MBUS_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = < RST_BUS_VE>;
+ interrupts = ;
+ allwinner,sram = <_sram 1>;
+ };
+
syscon: syscon@300 {
compatible = "allwinner,sun50i-h6-system-control",
"allwinner,sun50i-a64-system-control";
--
2.20.1
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[linux-sunxi] [PATCH 3/6] media: cedrus: Add support for H6
H6 has improved VPU. It supports 10-bit HEVC decoding and AFBC output
format for HEVC.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c
b/drivers/staging/media/sunxi/cedrus/cedrus.c
index ff11cbeba205..b98add3cdedd 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
@@ -396,6 +396,11 @@ static const struct cedrus_variant
sun50i_h5_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED,
};
+static const struct cedrus_variant sun50i_h6_cedrus_variant = {
+ .capabilities = CEDRUS_CAPABILITY_UNTILED,
+ .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET,
+};
+
static const struct of_device_id cedrus_dt_match[] = {
{
.compatible = "allwinner,sun4i-a10-video-engine",
@@ -425,6 +430,10 @@ static const struct of_device_id cedrus_dt_match[] = {
.compatible = "allwinner,sun50i-h5-video-engine",
.data = _h5_cedrus_variant,
},
+ {
+ .compatible = "allwinner,sun50i-h6-video-engine",
+ .data = _h6_cedrus_variant,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, cedrus_dt_match);
--
2.20.1
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[linux-sunxi] [PATCH 0/6] H6 Cedrus support
This patch series adds basic support for H6 VPU. VPU itself has some new features like 10-bit HEVC decoding, support for AFBC output format when decoding HEVC and IOMMU. However, none of that is currently implemented. Please take a look. Best regards, Jernej Jernej Skrabec (6): dt-bindings: media: cedrus: Add H6 compatible media: cedrus: Add a quirk for not setting DMA offset media: cedrus: Add support for H6 dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1 arm64: dts: allwinner: h6: Add support for the SRAM C1 section arm64: dts: allwinner: h6: Add Video Engine node .../devicetree/bindings/media/cedrus.txt | 1 + .../devicetree/bindings/sram/sunxi-sram.txt | 1 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 25 +++ drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +++ drivers/staging/media/sunxi/cedrus/cedrus.h | 3 +++ .../staging/media/sunxi/cedrus/cedrus_hw.c| 3 ++- 6 files changed, 41 insertions(+), 1 deletion(-) -- 2.20.1 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v3 6/8] drm/panel: simple: Add support for the LeMaker BL035-RGB-002 3.5" LCD
On Wed, Nov 07, 2018 at 07:18:41PM +0100, Paul Kocialkowski wrote: > This adds support for the 3.5" LCD panel from LeMaker, sold for use with > BananaPi boards. It comes with a 24-bit RGB888 parallel interface and > requires an active-low DE signal > > Signed-off-by: Paul Kocialkowski > --- > drivers/gpu/drm/panel/panel-simple.c | 27 +++ > 1 file changed, 27 insertions(+) Applied to drm-misc-next, thanks. Thierry -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v3 5/8] dt-bindings: Add bindings for the LeMaker BL035-RGB-002 LCD panel
On Wed, Nov 07, 2018 at 07:18:40PM +0100, Paul Kocialkowski wrote: > This adds the device-tree bindings for the LeMaker BL035-RGB-002 3.5" > QVGA TFT LCD panel, compatible with simple-panel. > > Signed-off-by: Paul Kocialkowski > --- > .../bindings/display/panel/lemaker,bl035-rgb-002.txt | 12 > 1 file changed, 12 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/panel/lemaker,bl035-rgb-002.txt Applied to drm-misc-next, thanks. Thierry -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v3 4/8] dt-bindings: Add vendor prefix for LeMaker
On Wed, Nov 07, 2018 at 07:18:39PM +0100, Paul Kocialkowski wrote: > This introduces a new device-tree binding vendor prefix for Shenzhen > LeMaker Technology Co., Ltd. > > This vendor was already in use but it was not documented until now. > > Signed-off-by: Paul Kocialkowski > Reviewed-by: Rob Hering > --- > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > 1 file changed, 1 insertion(+) Applied to drm-misc-next, thanks. Thierry -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v8 3/5] arm64: dts: allwinner: a64: Add A64 CSI controller
On Mon, Jan 28, 2019 at 02:28:45PM +0530, Jagan Teki wrote: > Add dts node details for Allwinner A64 CSI controller. > > A64 CSI has similar features as like in H3, but the CSI_SCLK > need to update it to 300MHz than default clock rate. > > Signed-off-by: Jagan Teki > Acked-by: Maxime Ripard Applied, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v8 2/5] media: sun6i: Add A64 CSI block support
On Mon, Jan 28, 2019 at 02:28:44PM +0530, Jagan Teki wrote: > CSI block in Allwinner A64 has similar features as like in H3, > but the default CSI_SCLK rate cannot work properly to drive the > connected sensor interface. > > The tested mod cock rate is 300 MHz and BSP vfe media driver is also > using the same rate. Unfortunately there is no valid information about > clock rate in manual or any other sources except the BSP driver. so more > faith on BSP code, because same has tested in mainline. > > So, add support for A64 CSI block by setting updated mod clock rate. > > Signed-off-by: Jagan Teki Acked-by: Maxime Ripard Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v6 11/22] clk: sunxi-ng: a64: Add minimum rate for PLL_MIPI
On Sat, Jan 26, 2019 at 2:54 AM Maxime Ripard wrote: > > On Fri, Jan 25, 2019 at 01:28:49AM +0530, Jagan Teki wrote: > > Minimum PLL used for MIPI is 500MHz, as per manual, but > > lowering the min rate by 300MHz can result proper working > > nkms divider with the help of desired dclock rate from > > panel driver. > > > > Signed-off-by: Jagan Teki > > Acked-by: Stephen Boyd > > Going 200MHz below the minimum doesn't seem really reasonable. What > is the issue that you are trying to fix here? > > It looks like it's picking bad dividers, but if that's the case, this > isn't the proper fix. As I stated in earlier patches, the whole idea is pick the desired dclk divider based dclk rate. So the dotclock, sun4i_dclk_round_rate is unable to get the proper dclk divider at the end, so it eventually picking up wrong divider value and fired vblank timeout. So, we come-up with optimal and working min_rate 300MHz in pll-mipi to get the desired clock something like below. [2.415773] [drm] No driver support for vblank timestamp query. [2.424116] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 5500 [2.424172] ideal = 22000, rounded = 0 [2.424176] ideal = 27500, rounded = 0 [2.424194] ccu_nkm_round_rate: rate = 33000 [2.424197] ideal = 33000, rounded = 33000 [2.424201] sun4i_dclk_round_rate: div = 6 rate = 5500 [2.424205] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 5500 [2.424209] ideal = 22000, rounded = 0 [2.424213] ideal = 27500, rounded = 0 [2.424230] ccu_nkm_round_rate: rate = 33000 [2.424233] ideal = 33000, rounded = 33000 [2.424236] sun4i_dclk_round_rate: div = 6 rate = 5500 [2.424253] ccu_nkm_round_rate: rate = 33000 [2.424270] ccu_nkm_round_rate: rate = 33000 [2.424278] sun4i_dclk_recalc_rate: val = 1, rate = 33000 [2.424281] sun4i_dclk_recalc_rate: val = 1, rate = 33000 [2.424306] ccu_nkm_set_rate: rate = 33000, parent_rate = 29700 [2.424309] ccu_nkm_set_rate: _nkm.n = 5 [2.424311] ccu_nkm_set_rate: _nkm.k = 2 [2.424313] ccu_nkm_set_rate: _nkm.m = 9 [2.424661] sun4i_dclk_set_rate div 6 [2.424668] sun4i_dclk_recalc_rate: val = 6, rate = 5500 But look like this wouldn't valid for all other dclock rates, say BPI panel has 30MHz clock that would failed with this logic. On the other side Allwinner BSP calculating dclk divider based on the SoC's. for A33 [1] it is fixed dclk divider of 4 and for A64 is is calculated based on the bpp/lanes. Since the above min_rate is not desired for possible panels clock, I think we can rely on BSP to make a move here. I'm planning to do these changes in next version. Let me know if you have any comments here? [1] https://patchwork.kernel.org/patch/10777519/ -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [DO NOT MERGE] [PATCH v8 5/5] arm64: dts: allwinner: bananapi-m64: Add HDF5640 camera module
Bananapi M64 comes with an optional sensor based on the ov5640,
add support for it with below pin information.
- PE13, PE12 via i2c-gpio bitbanging
- CLK_CSI_MCLK as external clock
- PE1 as external clock pin muxing
- DLDO3 as AVDD supply
- ALDO1 as DOVDD supply
- ELDO3 as DVDD supply
- PE16 gpio for reset pin
- PE17 gpio for powerdown pin
Signed-off-by: Jagan Teki
---
.../dts/allwinner/sun50i-a64-bananapi-m64.dts | 65 +++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 9d0afd7d50ec..c99f66271287 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -60,6 +60,41 @@
stdout-path = "serial0:115200n8";
};
+ i2c-csi {
+ compatible = "i2c-gpio";
+ sda-gpios = < 4 13 GPIO_ACTIVE_HIGH>; /* CSI0-SDA: PE13 */
+ scl-gpios = < 4 12 GPIO_ACTIVE_HIGH>; /* CSI0-SCK: PE12 */
+ i2c-gpio,delay-us = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_mclk_pin>;
+ clocks = < CLK_CSI_MCLK>;
+ clock-names = "xclk";
+
+ AVDD-supply = <_dldo3>;
+ DOVDD-supply = <_aldo1>;
+ DVDD-supply = <_eldo3>;
+ reset-gpios = < 4 16 GPIO_ACTIVE_LOW>; /* CSI0-RST:
PE16 */
+ powerdown-gpios = < 4 17 GPIO_ACTIVE_HIGH>; /*
CSI0-PWDN: PE17 */
+
+ port {
+ ov5640_ep: endpoint {
+ remote-endpoint = <_ep>;
+ bus-width = <8>;
+ hsync-active = <1>; /* Active high */
+ vsync-active = <0>; /* Active low */
+ data-active = <1>; /* Active high */
+ pclk-sample = <1>; /* Rising */
+ };
+ };
+ };
+ };
+
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
@@ -108,6 +143,24 @@
status = "okay";
};
+ {
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_ep: endpoint {
+ remote-endpoint = <_ep>;
+ bus-width = <8>;
+ hsync-active = <1>; /* Active high */
+ vsync-active = <0>; /* Active low */
+ data-active = <1>; /* Active high */
+ pclk-sample = <1>; /* Rising */
+ };
+ };
+};
+
{
status = "okay";
};
@@ -298,6 +351,12 @@
regulator-name = "vcc-wifi";
};
+_dldo3 {
+ regulator-min-microvolt = <280>;
+ regulator-max-microvolt = <280>;
+ regulator-name = "avdd-csi";
+};
+
_dldo4 {
regulator-min-microvolt = <180>;
regulator-max-microvolt = <330>;
@@ -315,6 +374,12 @@
regulator-name = "cpvdd";
};
+_eldo3 {
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <150>;
+ regulator-name = "dvdd-csi";
+};
+
_fldo1 {
regulator-min-microvolt = <120>;
regulator-max-microvolt = <120>;
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v8 3/5] arm64: dts: allwinner: a64: Add A64 CSI controller
Add dts node details for Allwinner A64 CSI controller.
A64 CSI has similar features as like in H3, but the CSI_SCLK
need to update it to 300MHz than default clock rate.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 839b2ae88583..62fdf850e9e5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -558,6 +558,12 @@
interrupt-controller;
#interrupt-cells = <3>;
+ csi_pins: csi-pins {
+ pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
+ "PE7", "PE8", "PE9", "PE10", "PE11";
+ function = "csi";
+ };
+
i2c0_pins: i2c0_pins {
pins = "PH0", "PH1";
function = "i2c0";
@@ -925,6 +931,20 @@
status = "disabled";
};
+ csi: csi@1cb {
+ compatible = "allwinner,sun50i-a64-csi";
+ reg = <0x01cb 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI_SCLK>,
+< CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = < RST_BUS_CSI>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "disabled";
+ };
+
hdmi: hdmi@1ee {
compatible = "allwinner,sun50i-a64-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi";
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v8 4/5] arm64: dts: allwinner: a64: Add pinmux setting for CSI MCLK on PE1
Some camera modules have the SoC feeding a master clock to the sensor
instead of having a standalone crystal. This clock signal is generated
from the clock control unit and output from the CSI MCLK function of
pin PE1.
Add a pinmux setting for it for camera sensors to reference.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 62fdf850e9e5..6e5a608f56f2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -564,6 +564,11 @@
function = "csi";
};
+ csi_mclk_pin: csi-mclk {
+ pins = "PE1";
+ function = "csi";
+ };
+
i2c0_pins: i2c0_pins {
pins = "PH0", "PH1";
function = "i2c0";
--
2.18.0.321.gffc6fa0e3
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[linux-sunxi] [PATCH v8 1/5] dt-bindings: media: sun6i: Add A64 CSI compatible
Allwinner A64 CSI is a single channel time-multiplexed BT.656 protocol interface. Add separate compatible string for A64 since it require explicit change in sun6i_csi driver to update default CSI_SCLK rate. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring Acked-by: Maxime Ripard --- Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt index cc37cf7fd051..0dd540bb03db 100644 --- a/Documentation/devicetree/bindings/media/sun6i-csi.txt +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt @@ -8,6 +8,7 @@ Required properties: * "allwinner,sun6i-a31-csi" * "allwinner,sun8i-h3-csi" * "allwinner,sun8i-v3s-csi" +* "allwinner,sun50i-a64-csi" - reg: base address and size of the memory-mapped region. - interrupts: interrupt associated to this IP - clocks: phandles to the clocks feeding the CSI -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v8 0/5] media/sun6i: Allwinner A64 CSI support
Add CSI support for Allwinner A64. Here is previous series[1] Changes for v8: - update proper enable and disable sequnce for clk_mod - fix warning for patch "media: sun6i: Add A64 CSI block support" - collect Maxime Acked-by Changes for v7: - Drop quirk change, and add as suggusted by Maxime - Use csi instead csi0 in pinctrl function Changes for v6: - set the mod rate in seett_power instead of probe Changes for v5: - Add mod_rate quirk for better handling clk_set code Changes for v4: - update the compatible string order - add proper commit message - included BPI-M64 patch - skipped amarula-a64 patch Changes for v3: - update dt-bindings for A64 - set mod clock via csi driver - remove assign clocks from dtsi - remove i2c-gpio opendrian - fix avdd and dovdd supplies - remove vcc-csi pin group supply [1] https://patchwork.kernel.org/cover/10779831/ Jagan Teki (5): dt-bindings: media: sun6i: Add A64 CSI compatible media: sun6i: Add A64 CSI block support arm64: dts: allwinner: a64: Add A64 CSI controller arm64: dts: allwinner: a64: Add pinmux setting for CSI MCLK on PE1 [DO NOT MERGE] arm64: dts: allwinner: bananapi-m64: Add HDF5640 camera module .../devicetree/bindings/media/sun6i-csi.txt | 1 + .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 65 +++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++ .../platform/sunxi/sun6i-csi/sun6i_csi.c | 11 4 files changed, 102 insertions(+) -- 2.18.0.321.gffc6fa0e3 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v8 2/5] media: sun6i: Add A64 CSI block support
CSI block in Allwinner A64 has similar features as like in H3,
but the default CSI_SCLK rate cannot work properly to drive the
connected sensor interface.
The tested mod cock rate is 300 MHz and BSP vfe media driver is also
using the same rate. Unfortunately there is no valid information about
clock rate in manual or any other sources except the BSP driver. so more
faith on BSP code, because same has tested in mainline.
So, add support for A64 CSI block by setting updated mod clock rate.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index ee882b66a5ea..5ecdfbf9f6ae 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -154,6 +155,7 @@ bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
int sun6i_csi_set_power(struct sun6i_csi *csi, bool enable)
{
struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
+ struct device *dev = sdev->dev;
struct regmap *regmap = sdev->regmap;
int ret;
@@ -161,6 +163,9 @@ int sun6i_csi_set_power(struct sun6i_csi *csi, bool enable)
regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, 0);
clk_disable_unprepare(sdev->clk_ram);
+ if (of_device_is_compatible(dev->of_node,
+ "allwinner,sun50i-a64-csi"))
+ clk_rate_exclusive_put(sdev->clk_mod);
clk_disable_unprepare(sdev->clk_mod);
reset_control_assert(sdev->rstc_bus);
return 0;
@@ -172,6 +177,9 @@ int sun6i_csi_set_power(struct sun6i_csi *csi, bool enable)
return ret;
}
+ if (of_device_is_compatible(dev->of_node, "allwinner,sun50i-a64-csi"))
+ clk_set_rate_exclusive(sdev->clk_mod, 3);
+
ret = clk_prepare_enable(sdev->clk_ram);
if (ret) {
dev_err(sdev->dev, "Enable clk_dram_csi clk err %d\n", ret);
@@ -191,6 +199,8 @@ int sun6i_csi_set_power(struct sun6i_csi *csi, bool enable)
clk_ram_disable:
clk_disable_unprepare(sdev->clk_ram);
clk_mod_disable:
+ if (of_device_is_compatible(dev->of_node, "allwinner,sun50i-a64-csi"))
+ clk_rate_exclusive_put(sdev->clk_mod);
clk_disable_unprepare(sdev->clk_mod);
return ret;
}
@@ -895,6 +905,7 @@ static const struct of_device_id sun6i_csi_of_match[] = {
{ .compatible = "allwinner,sun6i-a31-csi", },
{ .compatible = "allwinner,sun8i-h3-csi", },
{ .compatible = "allwinner,sun8i-v3s-csi", },
+ { .compatible = "allwinner,sun50i-a64-csi", },
{},
};
MODULE_DEVICE_TABLE(of, sun6i_csi_of_match);
--
2.18.0.321.gffc6fa0e3
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