On Thu, Oct 3, 2019 at 6:47 PM Maxime Ripard wrote:
>
> On Thu, Oct 03, 2019 at 12:15:21PM +0530, Jagan Teki wrote:
> > The LCD timing definitions between Linux DRM vs Allwinner are different,
> > below diagram shows this clear differences.
> >
> >Active Front
于 2019年10月3日 GMT+08:00 下午9:19:16, Maxime Ripard 写到:
>On Thu, Oct 03, 2019 at 12:38:43PM +0530, Jagan Teki wrote:
>> On Tue, Oct 1, 2019 at 1:33 PM Icenowy Zheng wrote:
>> >
>> > This reverts commit da676c6aa6413d59ab0a80c97bbc273025e640b2.
>> >
>> > The original commit adds a start parameter t
于 2019年10月3日 GMT+08:00 下午7:47:33, Maxime Ripard 写到:
>On Thu, Oct 03, 2019 at 12:15:24PM +0530, Jagan Teki wrote:
>> Allwinner MIPI DSI controllers are supplied with SoC DSI
>> power rails via VCC-DSI pin.
>>
>> Some board still work without supplying this but give more
>> faith on datasheet and
On Tue, Oct 1, 2019 at 1:33 PM Icenowy Zheng wrote:
>
> This reverts commit da676c6aa6413d59ab0a80c97bbc273025e640b2.
>
> The original commit adds a start parameter to the calculation of the
> start delay according to some old BSP versions from Allwinner. However,
> there're two ways to add this d
On Thu, Oct 3, 2019 at 12:26 PM Chen-Yu Tsai wrote:
>
> On Thu, Oct 3, 2019 at 2:46 PM Jagan Teki wrote:
> >
> > Allwinner MIPI DSI controllers are supplied with SoC
> > DSI power rails via VCC-DSI pin.
> >
> > Add support for this supply pin by adding voltage
> > regulator handling code to MIPI
