[linux-sunxi] [PATCH v3 6/9] dt-bindings: sun6i-dsi: Add R40 DPHY compatible (w/ A31 fallback)

The MIPI DSI PHY controller on Allwinner R40 is similar on the one on A31. Add R40 compatible and append A31 compatible as fallback. Signed-off-by: Jagan Teki --- Changes for v3: - update the binding in new yaml format .../devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 1 + 1

[linux-sunxi] [PATCH v3 8/9] ARM: dts: sun8i: r40: Add MIPI DSI pipeline

Add MIPI DSI pipeline for Allwinner R40. Unlike conventional Display pipeline in allwinner, R40 have TCON TCOP which would interact various block like muxes, tcon lcd, tcon_tv for better pipeline fitting. For MIPI DSI pipeline, we have to configure the tcon_lcd0 block which would interact with

[linux-sunxi] [PATCH v3 3/9] ARM: dts: sun8i: r40: Use tcon top clock index macros

tcon_tv0, tcon_tv1 nodes have a clock names of tcon-ch0, tcon-ch1 which are referring tcon_top clocks via index numbers like 0, 1 with CLK_TCON_TV0 and CLK_TCON_TV1 respectively. Use the macro in place of index numbers, for more code readability. Signed-off-by: Jagan Teki Reviewed-by: Chen-Yu

[linux-sunxi] [PATCH v3 4/9] drm/sun4i: tcon_top: Use clock name index macros

TCON TOP mux blocks in R40 are registering clock using tcon top clock index numbers. Right now the code is using, real numbers start with 0, but we have proper macros that defined these name index numbers. Use the existing macros, instead of real numbers for more code readability.

[linux-sunxi] [PATCH v3 5/9] drm/sun4i: tcon_top: Register reset, clock gates in probe

TCON TOP is processing clock gates and reset control for TV0, TV1 and DSI channels during bind and release the same during unbind component ops. The usual DSI initialization would setup all controller clocks along with DPHY clocking during probe. Since the actual clock gates (along with DSI

[linux-sunxi] [DO NOT MERGE] [PATCH v3 9/9] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable Bananapi S070WV20-CT16

This patch add support for Bananapi S070WV20-CT16 DSI panel to BPI-M2U board. DSI panel connected via board DSI port with, - DCDC1 as VCC-DSI supply - PH18 gpio for lcd enable pin - PD17 gpio for lcd reset pin - PD16 gpio for backlight enable pin Signed-off-by: Jagan Teki --- Changes for v3: -

[linux-sunxi] [PATCH v3 7/9] dt-bindings: sun6i-dsi: Document R40 MIPI-DSI controller (w/ A64 fallback)

The MIPI DSI controller on Allwinner R40 is similar on the one on A64 like doesn't associate any DSI_SCLK gating. So, add R40 compatible and append A64 compatible as fallback. Signed-off-by: Jagan Teki --- Changes for v3: - update the binding in new yaml format

[linux-sunxi] [PATCH v3 0/9] drm/sun4i: Allwinner R40 MIPI-DSI support

This is v3 version for supporting MIPI-DSI on Allwinner R40 from initial version[1]. The controller look similar like, Allwinner A64 but with associated R40 TCON TOP for DSI pipeline. Changes for v3: - collect Rob, Chen-Yu r-b, a-b tags - move tcon top reset control methods into probe - rebase

[linux-sunxi] [PATCH v3 2/9] drm/sun4i: tcon: Add TCON LCD support for R40

TCON LCD0, LCD1 in allwinner R40, are used for managing LCD interfaces like RGB, LVDS and DSI. Like TCON TV0, TV1 these LCD0, LCD1 are also managed via tcon top. Add support for it, in tcon driver. Signed-off-by: Jagan Teki --- Changes for v3: - none drivers/gpu/drm/sun4i/sun4i_tcon.c | 8

[linux-sunxi] [PATCH v3 1/9] dt-bindings: display: Add TCON LCD compatible for R40

Like TCON TV0, TV1 allwinner R40 has TCON LCD0, LCD1 which are managed via TCON TOP. Add tcon lcd compatible R40, the same compatible can handle TCON LCD0, LCD1. Signed-off-by: Jagan Teki Acked-by: Chen-Yu Tsai Reviewed-by: Rob Herring --- Changes for v3: - none