Hi Andre,
thanks for working on this!
Dne petek, 20. november 2020 ob 10:42:15 CET je André Przywara napisal(a):
> On 19/11/2020 19:59, Priit Laes wrote:
> > On Thu, Nov 19, 2020 at 10:54:42AM +, Andre Przywara wrote:
> >> So far we did not support the BootROM based FEL USB debug mode on the
Maxime,
On 11/20/20 5:30 PM, Icenowy Zheng wrote:
>>> +/ {
>>> + model = "PineTab Developer Sample";
>>> + compatible = "pine64,pinetab-dev", "allwinner,sun50i-a64";
>>> +};
>>
>> Changing the DT and the compatible half-way through it isn't ok. Please
>>
于 2020年11月20日 GMT+08:00 下午11:59:39, Maxime Ripard 写到:
>On Tue, Nov 17, 2020 at 02:36:48AM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2020年11月16日 GMT+08:00 下午11:55:08, Maxime Ripard
>写到:
>> >On Tue, Nov 10, 2020 at 06:41:37PM +0800, Icenowy Zheng wrote:
>> >>
>> >>
>> >> 于 2020年11月10日
On Fri, Nov 20, 2020 at 01:08:51PM +0800, Icenowy Zheng wrote:
> Currently the GIC node in V3s DTSI follows some old DT examples, and
> being broken. This leads a warning at boot.
>
> Fix this.
>
> Fixes: f989086ccbc6 ("ARM: dts: sunxi: add dtsi file for V3s SoC")
> Signed-off-by: Icenowy Zheng
On Tue, Nov 17, 2020 at 02:36:48AM +0800, Icenowy Zheng wrote:
>
>
> 于 2020年11月16日 GMT+08:00 下午11:55:08, Maxime Ripard 写到:
> >On Tue, Nov 10, 2020 at 06:41:37PM +0800, Icenowy Zheng wrote:
> >>
> >>
> >> 于 2020年11月10日 GMT+08:00 下午6:39:25, Maxime Ripard
> >写到:
> >> >On Sat, Nov 07, 2020 at
On Mon, Nov 09, 2020 at 01:33:57PM +0800, Icenowy Zheng wrote:
> According to the user manual, PLL-CPUX have two dividers, in which P is
> only allowed when the desired rate is less than 240MHz. As the CCU
> framework have no such feature yet and the clock rate that allows P is
> much lower than
On Mon, Nov 09, 2020 at 01:33:56PM +0800, Icenowy Zheng wrote:
> According to Ondrej Jirman, switching of the mux of CPUX clock is one of
> the sources of timer jumps on A64 (and maybe this will also lead to
> timer jump on H3).
Isn't the arch timer supposed to be clocked directly for the 24MHz
On 19/11/2020 19:59, Priit Laes wrote:
> On Thu, Nov 19, 2020 at 10:54:42AM +, Andre Przywara wrote:
>> So far we did not support the BootROM based FEL USB debug mode on the
>> 64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but the
>> SPL runs in AArch64.
>> Returning back to
