i use spidev for receiving data from spi0
for low speed it works
./spidev_fdx /dev/spidev0.0 -r 16
/dev/spidev0.0: spi mode 0x0, 8 bits per word, 5 Hz max
read(16, 16): 01 56, 0c 24 b8 06 70 03 b0 b6 ff 66 03 b0 c4 ff
but for higher speed i get nothings and all data is zero
./spidev_fdx
在 2020-12-14星期一的 01:35 +，André Przywara写道：
> On 13/12/2020 18:24, Icenowy Zheng wrote:
> > 在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
> > > Newer SoCs (A100, H616) need to clear a different bit in our
> > > "unknown"
> > > PMU PHY register.
> >
> > It looks like that the unknown PHY
On 13/12/2020 18:24, Icenowy Zheng wrote:
> 在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
>> Newer SoCs (A100, H616) need to clear a different bit in our
>> "unknown"
>> PMU PHY register.
>
> It looks like that the unknown PHY register is PHYCTL register for each
> individual PHY, and the bit
On 13/12/2020 17:47, Icenowy Zheng wrote:
Hi Icenowy,
> 在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
>> Hi,
>>
>> this is the quite expanded second version of the support series for
>> the
>> Allwinner H616 SoC.
>> Besides many fixes for the bugs discovered by the diligent reviewers
>> (many
As there is an RSB controller in the H6 SoC, there should be some pin
configuration for it. While no such configuration is documented, the
"s_i2c" pins are suspiciously on the "alternate" function 3, with no
primary function 2 given. This suggests the primary function for these
pins is actually
The H6 SoC contains an undocumented but fully functional RSB controller.
Add support for it. The MMIO register address matches other SoCs of the
same generation, and the IRQ matches a hole in the documented IRQ list.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
While no information about the H6 RSB controller is included in the
datasheet or manual, the vendor BSP and power management blob both
reference the RSB clock parent and register address. These values were
verified by experimentation.
Since this clock/reset are added late, the specifier is added
The Allwinner H6 SoC contains an RSB controller. It is almost completely
undocumented, so it was missed when doing the initial SoC bringup.
This series adds the clock/reset, pin configuration, and device tree
node needed to use the RSB controller. Since RSB is faster, simpler, and
generally more
On boards where the only peripheral connected to PL0/PL1 is an X-Powers
PMIC, configure the connection to use the RSB bus rather than the I2C
bus. Compared to the I2C controller that shares the pins, the RSB
controller allows a higher bus frequency, and it is more CPU-efficient.
Signed-off-by:
在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
> Newer SoCs (A100, H616) need to clear a different bit in our
> "unknown"
> PMU PHY register.
It looks like that the unknown PHY register is PHYCTL register for each
individual PHY, and the bit that is cleared is
called SUNXI_HCI_PHY_CTRL_SIDDQ in
在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
> Hi,
>
> this is the quite expanded second version of the support series for
> the
> Allwinner H616 SoC.
> Besides many fixes for the bugs discovered by the diligent reviewers
> (many thanks for that!) this version adds some patches to support
>
在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
> Port A is used for an internal connection to some analogue circuitry
> which looks like an AC200 IP (as in the H6), though this is not
> mentioned in the manual.
When developing for V831, I found that PIO controller in H616 (and
V831) has the
On Fri, Dec 11, 2020 at 01:19:29AM +, Andre Przywara wrote:
> From: Yangtao Li
>
> Add a binding for A100's watchdog controller.
>
> Signed-off-by: Yangtao Li
> Acked-by: Rob Herring
> Signed-off-by: Andre Przywara
Reviewed-by: Guenter Roeck
> ---
>
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