On Thu, Feb 25, 2021 at 3:17 PM André Przywara wrote:
>
> On 20/02/2021 12:14, Nicolas Boulenguez wrote:
> > From: Marius Gripsgard
>
> Hi,
>
> This is not really Pinephone specific, actually not even sunxi specific.
> I see two better ways of solving this:
>
> - We introduce some generic code
Previously we do not have proper dual rank memory detection on R40
(because we omitted PIR_QSGATE, which does not work on R40 with our
configuration), and dual rank memory is just simply disabled as early
R40 boards available (Banana Pi M2 Ultra and Berry) have single rank
memory.
As a board with
Previously we have known that R40 has a configuration register for its
rank 1, which allows different configuration than rank 0. Reverse
engineering of newest libdram of A64 from Allwinner shows that A64 has
this register too. It's bit 0 (which enables dual rank in rank 0
configuration register)
This patchset contains two patches.
The first one enables asymmetric dual rank DRAM on A64. This is needed
for 3GiB PinePhone, which has 2GiB rank 0 and 1GiB rank 1. This patch is
already used by the firmware flashed to PinePhone by factory.
The second one enables dual rank (and asymmetric dual
On 20/02/2021 12:14, Nicolas Boulenguez wrote:
> From: Marius Gripsgard
Hi,
This is not really Pinephone specific, actually not even sunxi specific.
I see two better ways of solving this:
- We introduce some generic code to find "gpio-leds" subnodes in the DT,
which have a default-state = "on"
On Wed, Feb 24, 2021 at 11:52:38AM +0100, Pascal Roeleven wrote:
> On request I'm resending the last two patches from the Topwise A721 tablet
> series from a year ago as they weren't picked up. The other patches are
> already merged, so I didn't resend them.
>
> Changes from v4:
> * Reorder nodes
