The GPIO-based bitbanging I2C driver is required to configure
CSI data, clock pins on CSI block in Allwinner A64 SoC.
Let build it as module.
Signed-off-by: Jagan Teki
---
Note:
- These change depends on A64 CSI support patches
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion
On Mon, Jan 21, 2019 at 4:12 PM Chen-Yu Tsai wrote:
>
> On Mon, Jan 21, 2019 at 6:32 PM Jagan Teki wrote:
> >
> > Environment and fastboot MMC devices are configured based number
> > of mmc slots defined on particular board in sunxi platform.
> >
> > If num
Now CLK and RESET driver for Allwinner SoC are available,
so add the relevant operations on mmc sunxi driver.
Cc: Jaehoon Chung
Signed-off-by: Jagan Teki
---
Changes for v3:
- Grab changes for ML
drivers/mmc/sunxi_mmc.c | 52 +
1 file changed, 47
DM_MMC game.
Signed-off-by: Andre Przywara
[jagan: fix a80 mmc clock config compatible]
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a80.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi
Unlike other Allwinner SoC's, H6 comes with different
clock and reset control offset values. So support them
via driver data.
Cc: Jaehoon Chung
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/mmc/sunxi_mm
Enable DM_MMC for all Allwinner SoCs, this will eventually
enable BLK.
Also removed DM_MMC enablement in few parts of sunxi
configurations.
Signed-off-by: Jagan Teki
---
arch/arm/Kconfig | 1 +
arch/arm/mach-sunxi/Kconfig | 1 -
configs
if the board dts has mmc0, mmc1, mmc2.
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for
enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki
---
arch/arm/dts/sunxi-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch
Add emmc compatible for A83T SoC.
Cc: Jaehoon Chung
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 302332bf97..ec4f227130 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers
Added H5, A64 compatible for mmc and emmc.
Cc: Jaehoon Chung
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index ec4f227130..1259e627cc 100644
--- a/drivers/mmc/sunxi_mmc.c
, fix CLK_AHB1_MMC3 bit]
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a10.c | 4
drivers/clk/sunxi/clk_a10s.c | 3 +++
drivers/clk/sunxi/clk_a23.c | 6 ++
drivers/clk/sunxi/clk_a31.c | 8
drivers/clk/sunxi/clk_a64.c | 6 ++
drivers/clk/sunxi/clk_a83t.c | 6 ++
drivers/clk/
framework.
Changes for v2:
- update the 'reset enablement' logic to do
required SoC's
[1] https://patchwork.ozlabs.org/cover/1026828/
[2] https://patchwork.ozlabs.org/cover/1027850/
Andre Przywara (2):
sunxi: clk: add MMC gates/resets
sunxi: clk: A80: add MMC clock support
Unlike other Allwinner SoC's, A80 comes with different ahb
gate clock offset values and also has mmc common controller.
So support them via driver data.
Cc: Rask Ingemann Lambertsen
Cc: Jaehoon Chung
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 8
1 file chang
On Sat, Jan 19, 2019 at 7:02 AM Andre Przywara wrote:
>
> The A80 handles resets and clock gates for the MMC devices differently,
> outside of the CCU IP block. Consequently we have a separate clock
> device with a separate binding for that.
>
> Implement that with the respective clock gates and r
On Sat, Jan 19, 2019 at 7:02 AM Andre Przywara wrote:
>
> This series enables the Allwinner MMC driver to drive all SoCs with its
> DM_MMC variant. We use the gates clock and reset support from the new
> clock driver, but keep the actual mod clock in its somewhat hackish
> state. Properly supporti
On Fri, Jan 18, 2019 at 11:18 PM Andre Przywara wrote:
>
> On Fri, 18 Jan 2019 22:11:36 +0530
> Jagan Teki wrote:
>
> Hi,
>
> > On Fri, Jan 18, 2019 at 6:00 PM Andre Przywara
> > wrote:
> > >
> > > On Fri, 18 Jan 2019 07:17:41 -0500
> > &g
On Fri, Jan 11, 2019 at 4:48 PM Jagan Teki wrote:
>
> CLK and DM_RESET drivers are now available for all of
> the Allwinner platforms, so enable them in arch/arm/Kconfig
>
> Enabling CLK will select DM_RESET by default.
>
> Signed-off-by: Jagan Teki
> ---
Applied to u-bo
On Fri, Jan 11, 2019 at 12:13 AM Jagan Teki wrote:
>
> This series fixes few comments from previous verision for Allwinner
> clock gates, resets and dropped clock tree patches which I have
> mentioned on previous series[1].
>
> Changes for v6:
> - use ARRAY_SIZE for reset ar
On Fri, Jan 11, 2019 at 4:46 PM Jagan Teki wrote:
>
> Update all A80 devicetree dtsi and dtsi files from
> Linux-v4.18-rc3 with below commits.
>
> arch/arm/boot/dts/sun9i-a80*:
>
> commit 190e3138f9577885691540dca59c2f07540bde04
> Merge: cafc87023b0d a7affb13b271
> Au
On Fri, Jan 18, 2019 at 6:00 PM Andre Przywara wrote:
>
> On Fri, 18 Jan 2019 07:17:41 -0500
> Tom Rini wrote:
>
> > On Fri, Jan 18, 2019 at 11:53:49AM +, Andre Przywara wrote:
> > > On Thu, 17 Jan 2019 22:39:44 +0530
> > > Jagan Teki wrote:
> > &g
Add dts node details for Allwinner A64 CSI controller.
A64 CSI has similar features as like in H3, but the CSI_SCLK
need to update it to 300MHz than default clock rate.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++
1 file changed, 20
CSI block in Allwinner A64 has similar features as like in H3,
but default mod clock rate in BSP along with latest mainline testing
require to operate it at 300MHz.
So, add A64 CSI compatibe along with mod_rate quirk.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi
clock rate.
Signed-off-by: Jagan Teki
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 26 ---
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index ee
-csi pin group supply
[1] https://patchwork.kernel.org/cover/10738841/
Jagan Teki (6):
dt-bindings: media: sun6i: Add A64 CSI compatible
media: sun6i: Add mod_rate quirk
media: sun6i: Add A64 CSI block support
arm64: dts: allwinner: a64: Add A64 CSI controller
arm64: dts: allwinner: a64
On Thu, Jan 17, 2019 at 10:02 AM Jagan Teki wrote:
>
> On Thu, Jan 17, 2019 at 12:48 AM Maxime Ripard
> wrote:
> >
> > On Sun, Jan 13, 2019 at 01:07:41AM +0530, Jagan Teki wrote:
> > > > > > > > Again, I cannot help you without the dat
Enable DM_MMC for all Allwinner SoCs, this will eventually
enable BLK.
Also removed DM_MMC enablement in few parts of sunxi
configurations.
Signed-off-by: Jagan Teki
---
arch/arm/Kconfig | 1 +
arch/arm/mach-sunxi/Kconfig | 1 -
configs
if the board dts has mmc0, mmc1, mmc2.
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for
enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki
---
arch/arm/dts/sunxi-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch
Unlike other Allwinner SoC's, H6 comes with different
clock and reset control offset values. So support them
via driver data.
Signed-off-by: Jagan Teki
---
.../arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 3 +++
drivers/mmc/sunxi_mmc.c | 16
2
Unlike other Allwinner SoC's, A80 comes with different ahb
gate clock offset values and also has mmc common controller.
So support them via driver data.
Cc: Rask Ingemann Lambertsen
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 24
1 file change
Start with Allwinner A31, mmc controllers do support reset
control bit. This code add support to enable the reset control
start from SUN6I even though it share same compatible between
SUN4I and SUN6I.
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 21 +++--
1 file
Added H5, A64 compatible for mmc and emmc.
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index c25967afd1..b1c177bba3 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc
Add emmc compatible for A83T SoC.
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 0e53701c5b..c25967afd1 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
V2 for previous version[1] changes, for enabling DM_MMC
on Allwinner platform.
Changes for v2:
- update the 'reset enablement' logic to do
required SoC's
Note: All changes available at u-boot-sunxi/next
[1] https://patchwork.ozlabs.org/cover/1023710/
Any comments?
Jag
On Thu, Jan 17, 2019 at 12:48 AM Maxime Ripard
wrote:
>
> On Fri, Jan 11, 2019 at 11:54:12AM +0530, Jagan Teki wrote:
> > On Mon, Jan 7, 2019 at 6:59 PM Maxime Ripard
> > wrote:
> > > On Mon, Dec 24, 2018 at 08:57:48PM +0530, Jagan Teki wrote:
> > > >
On Thu, Jan 17, 2019 at 12:48 AM Maxime Ripard
wrote:
>
> On Sun, Jan 13, 2019 at 01:07:41AM +0530, Jagan Teki wrote:
> > > > > > > Again, I cannot help you without the datasheet for the panels
> > > > > > > you're
> > > > >
On Mon 14 Jan, 2019, 3:53 PM Priit Laes On Mon, Jan 14, 2019 at 03:40:37PM +0530, Jagan Teki wrote:
> > On Mon, Jan 14, 2019 at 3:05 PM Priit Laes wrote:
> > >
> > > On Fri, Jan 11, 2019 at 11:34:07PM +0530, Jagan Teki wrote:
> > > > I thought of waiting t
On Mon, Jan 14, 2019 at 3:05 PM Priit Laes wrote:
>
> On Fri, Jan 11, 2019 at 11:34:07PM +0530, Jagan Teki wrote:
> > I thought of waiting this till CLK framework gets Mainline,
> > but migration deadline for DM_MMC and BLK seems expiring in
> > next release. So instead
On Sat, Jan 12, 2019 at 10:13 PM Maxime Ripard
wrote:
>
> On Wed, Jan 09, 2019 at 06:57:57PM +0530, Jagan Teki wrote:
> > On Tue, Jan 8, 2019 at 2:28 PM Maxime Ripard
> > wrote:
> > >
> > > On Mon, Jan 07, 2019 at 08:48:21PM +0530, Jagan Teki wrote:
> >
On Sat, Jan 12, 2019 at 5:32 AM Vasily Khoruzhick wrote:
>
> On Fri, Jan 11, 2019 at 10:04 AM Jagan Teki
> wrote:
> >
> > I thought of waiting this till CLK framework gets Mainline,
> > but migration deadline for DM_MMC and BLK seems expiring in
> > next relea
SoC's and enable at arch/arm/Kconfig.
I shall merge this in comming MW, so early test feel better
to go for the release. Request to test respective board takers.
Any inputs,
Jagan.
Jagan Teki (7):
mmc: sunxi: Configure reset support for DM_MMC
mmc: sunxi: Add A83T emmc compatible
mmc:
Unlike other Allwinner SoC's, A80 comes with different ahb
gate clock offset values and also has mmc common controller.
So support them via driver data.
Cc: Rask Ingemann Lambertsen
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 24
1 file change
Add emmc compatible for A83T SoC.
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 0b17e2c391..5557111c1f 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
Added H5, A64 compatible for mmc and emmc.
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 5557111c1f..b50d70645a 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc
Enable DM_MMC for all Allwinner SoCs, this will eventually
enable BLK.
Also removed DM_MMC enablement in few parts of sunxi
configurations.
Signed-off-by: Jagan Teki
---
arch/arm/Kconfig | 1 +
arch/arm/mach-sunxi/Kconfig | 1 -
configs
Unlike other Allwinner SoC's, H6 comes with different
clock and reset control offset values. So support them
via driver data.
Signed-off-by: Jagan Teki
---
.../arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 3 +++
drivers/mmc/sunxi_mmc.c | 16
2
if the board dts has mmc0, mmc1, mmc2.
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for
enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki
---
arch/arm/dts/sunxi-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch
SoC's and enable at arch/arm/Kconfig.
I shall merge this in comming MW, so early test feel better
to go for the release. Request to test respective board takers.
Any inputs,
Jagan.
Jagan Teki (7):
mmc: sunxi: Configure reset support for DM_MMC
mmc: sunxi: Add A83T emmc compatible
mmc:
Start with Allwinner A31, mmc controllers do support reset
control bit. This code add support to enable the reset control
start from SUN6I even though it share same compatible between
SUN4I and SUN6I.
Signed-off-by: Jagan Teki
---
drivers/mmc/sunxi_mmc.c | 21 +++--
1 file
On Fri, Jan 11, 2019 at 5:54 PM Tom Rini wrote:
>
> On Fri, Jan 11, 2019 at 12:46:36PM +0530, Jagan Teki wrote:
> > On Sat, Dec 22, 2018 at 7:06 AM Andre Przywara
> > wrote:
> > >
> > > So far we used the separate mksunxiboot tool for generating a boo
On Fri, Jan 11, 2019 at 8:41 PM Zoltan HERPAI wrote:
>
> Hi,
>
> Jagan Teki wrote:
> >>> A20, can boot as it is, it doesn't effect mmc node on DT, since DM_MMC
> >>> is not available.
> >>>
> That's interesting, the Linksprite_pcDui
Chen-Yu and Rask,
On Fri, Jan 11, 2019 at 4:46 PM Jagan Teki wrote:
>
> Update all A80 devicetree dtsi and dtsi files from
> Linux-v4.18-rc3 with below commits.
>
> arch/arm/boot/dts/sun9i-a80*:
>
> commit 190e3138f9577885691540dca59c2f07540bde04
> Merge: cafc87023b0d a7a
CLK and DM_RESET drivers are now available for all of
the Allwinner platforms, so enable them in arch/arm/Kconfig
Enabling CLK will select DM_RESET by default.
Signed-off-by: Jagan Teki
---
Changes for v6.1:
- Enable CLK at one place since all Allwinner SoC's supported
arch/arm/Kconfi
> diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c
> new file mode 100644
> index 00..9b38149280
> --- /dev/null
> +++ b/tools/sunxi_egon.c
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2018 Arm Ltd.
> + */
> +
> +#i
On Sat, Dec 22, 2018 at 7:06 AM Andre Przywara wrote:
>
> At the moment "mkimage -T list" starts with two unknown entries, because
> their IH_TYPE_ name is not listed in the uimage_type table.
>
> Add those two entries to get an OCD-compatible image type listing.
>
> Signed-off-by: Andre Przywara
On Mon, Jan 7, 2019 at 6:59 PM Maxime Ripard wrote:
>
> On Mon, Dec 24, 2018 at 08:57:48PM +0530, Jagan Teki wrote:
> > On Fri, Dec 21, 2018 at 6:30 PM Maxime Ripard
> > wrote:
> > >
> > > On Thu, Dec 20, 2018 at 06:24:34PM +0530, Jagan Teki wrote:
> &g
On Mon, Jan 7, 2019 at 6:59 PM Maxime Ripard wrote:
>
> On Mon, Dec 24, 2018 at 08:57:48PM +0530, Jagan Teki wrote:
> > On Fri, Dec 21, 2018 at 6:30 PM Maxime Ripard
> > wrote:
> > >
> > > On Thu, Dec 20, 2018 at 06:24:34PM +0530, Jagan Teki wrote:
> &g
Hi,
On Wed, Jul 11, 2018 at 8:34 PM Daniel Vetter wrote:
>
> On Wed, Jul 11, 2018 at 4:52 PM, Noralf Trønnes wrote:
> >
> > Den 11.07.2018 16.06, skrev Maxime Ripard:
> >>
> >> CC'ing Noralf and Daniel,
> >>
> >> On Wed, Jul 11, 2018 at 09:47:53PM +0800, Icenowy Zheng wrote:
> >>>
> >>> Today, d
CLK and DM_RESET drivers are now available for most
of the Allwinner platforms, so enable in mach-sunxi/Kconfig
Enabling CLK will select DM_RESET by default.
Signed-off-by: Jagan Teki
---
arch/arm/mach-sunxi/Kconfig | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on phy driver.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
Reviewed-by: Marek Vasut
---
drivers/phy/allwinner/phy-sun4i-usb.c | 77 ---
1 file changed, 57 insertions(+
Add reset_valid to check whether given reset is valid
or not.
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
include/reset.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/reset.h b/include/reset.h
index bc495a90c2..65aa7a4ce5 100644
--- a/include/reset.h
+++ b/include
Now Allwinner platform is all set to use Generic USB
controller drivers, so remove the legacy sunxi drivers.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/usb/host/Makefile | 2 -
drivers/usb/host/ehci-sunxi.c | 204 -
drivers/usb/host/ohci
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on musb driver.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
Reviewed-by: Marek Vasut
---
drivers/usb/musb-new/sunxi.c | 79 ++--
1 file changed, 39 insertions(+
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
configs/A10-OLinuXino-Lime_defconfig | 1 +
configs/A10s-OLinuXino-M_defconfig| 1 +
configs/A13-OLinuXinoM_defconfig | 1 +
configs/A13-OLinuXino_defconfig | 1 +
configs/A20-OLinuXino-Lime2
patch from
commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691
Author: Andre Przywara
Date: Mon Oct 29 00:56:47 2018 +
sunxi: A64: Update .dts/.dtsi files
Signed-off-by: Jagan Teki
---
include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a23.c | 6 ++
drivers/clk/sunxi/clk_a31.c | 7 +++
drivers/clk/sunxi/clk_a64.c | 6 ++
drivers/clk/sunxi/clk_a83t.c | 6 ++
drivers/clk
functions from reset-sunxi.c
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/Kconfig | 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_h6.c | 53 ++
3 files changed, 61 insertions(+)
create mode 100644 drivers/clk/sunxi/clk_h6.c
diff
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_r40.c | 70 +
3 files changed, 78 insertions(+)
create mode
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a10.c | 9 +
drivers/clk/sunxi/clk_a10s.c | 5 +
drivers/clk/sunxi/clk_a23.c | 6 ++
drivers/clk/sunxi/clk_a31.c | 7 +++
drivers/clk
deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_v3s.c | 51 +
3 files changed, 59 insertions(+)
create
deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig| 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a83t.c | 63
3 files changed, 71 insertions(+)
create
deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a31.c | 68 +
3 files changed, 76 insertions(+)
create
common reset deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a23.c | 63 +
3 files changed, 71 insertions
deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig| 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a10s.c | 56
3 files changed, 64 insertions
reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_h3.c | 79 ++
3 files changed, 87 insertions(+)
create
deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a10.c | 59 +
3 files changed, 67 insertions(+)
create
table defined from
CLK driver.
Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/ccu.h | 33 ++-
drivers/clk/sunxi/Kc
CONFIG_USB_OHCI_HCD on few missing boards
- collect Marek Acked-by
Any inputs,
Jagan.
[1] https://patchwork.ozlabs.org/cover/1019654/
Jagan Teki (20):
clk: Add Allwinner A64 CLK driver
reset: Add Allwinner RESET driver
clk: sunxi: Add Allwinner H3/H5 CLK driver
clk: sunxi: Add Allwinner A10/A20 CLK
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/ccu.h | 65
On Thu, Jan 10, 2019 at 6:21 AM André Przywara wrote:
>
> On 08/01/2019 19:12, Jagan Teki wrote:
> > On Tue, Jan 8, 2019 at 5:09 PM Andre Przywara
> > wrote:
> >>
> >> On Tue, 8 Jan 2019 16:27:14 +0530
> >> Jagan Teki wrote:
> >>
&g
On Wed, Jan 9, 2019 at 1:08 AM Priit Laes wrote:
>
> On Tue, Jan 08, 2019 at 11:54:32PM +0530, Jagan Teki wrote:
> > On Thu, Jan 3, 2019 at 9:33 PM Zoltan HERPAI wrote:
> > >
> > > Hi Jagan, Adam,
> > >
> > > On Thu, 3 Jan 2019, Jagan Teki wro
On Tue, Jan 8, 2019 at 5:09 PM Andre Przywara wrote:
>
> On Tue, 8 Jan 2019 16:27:14 +0530
> Jagan Teki wrote:
>
> Hi,
>
> > On Mon, Jan 7, 2019 at 6:35 AM André Przywara
> > wrote:
> > >
> > > On 31/12/2018 16:59, Jagan Teki wrote:
> > &g
table defined from
CLK driver.
Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
Changes for v5.1:
- s/CCU_CLK_F_INIT_DONE/CCU_CLK_F_IS_VALID
- Add CCU_RST_F_IS_VALID
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
Changes for v5.1:
- s/CCU_CLK_F_INIT_DONE/CCU_CLK_F_IS_VALID
- Use
On Thu, Jan 3, 2019 at 9:33 PM Zoltan HERPAI wrote:
>
> Hi Jagan, Adam,
>
> On Thu, 3 Jan 2019, Jagan Teki wrote:
>
> > On Thu, Jan 3, 2019 at 6:57 PM Zoltan HERPAI wrote:
> >>
> >> Hi all,
> >>
> >> The DTS resync between 2018.09 and
On Mon, Jan 7, 2019 at 6:35 AM André Przywara wrote:
>
> On 31/12/2018 16:59, Jagan Teki wrote:
> > Clock control unit comprises of parent clocks, gates, multiplexers,
> > dividers, multipliers, pre/post dividers and flags etc.
> >
> > So, the U-Boot implementation
On Mon, Jan 7, 2019 at 6:35 AM André Przywara wrote:
>
> On 31/12/2018 16:59, Jagan Teki wrote:
> > Clock control unit comprises of parent clocks, gates, multiplexers,
> > dividers, multipliers, pre/post dividers and flags etc.
> >
> > So, the U-Boot implementation
On Mon, Jan 7, 2019 at 7:42 PM Maxime Ripard wrote:
>
> On Fri, Dec 21, 2018 at 02:26:11AM +0530, Jagan Teki wrote:
> > On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
> > wrote:
> > >
> > > On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> >
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on musb driver.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
Changes for v5.1:
- use dev_err instead of pr_err
drivers/usb/musb-new/sunxi.c | 79 ++--
1
On Sun, Jan 6, 2019 at 6:49 PM André Przywara wrote:
>
> On 31/12/2018 16:59, Jagan Teki wrote:
>
> Hi Jagan,
>
> many thanks for picking this up, I was about to come back to this
> myself. I am looking at the pinctrl part at the moment, so good you are
> working on the
On Mon, Dec 24, 2018 at 8:57 PM Jagan Teki wrote:
>
> On Fri, Dec 21, 2018 at 6:30 PM Maxime Ripard
> wrote:
> >
> > On Thu, Dec 20, 2018 at 06:24:34PM +0530, Jagan Teki wrote:
> > > Unfortunately default CSI_SCLK rate cannot work properly to
> > &g
On Fri, Dec 21, 2018 at 2:26 AM Jagan Teki wrote:
>
> On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
> wrote:
> >
> > On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > > Video start delay can be computed by subtracting total vertical
> > >
On Mon, Dec 31, 2018 at 10:30 PM Jagan Teki wrote:
>
> Although the previous version[1] is properly handled the clock gates
> with enable and disable management, but this series is trying to add
> some more complex Allwinner CLK architecture by handling parent clock
> and other
On Thu, Jan 3, 2019 at 6:57 PM Zoltan HERPAI wrote:
>
> Hi all,
>
> The DTS resync between 2018.09 and 2018.11 seems to have broken the MMC
> support for the Linksprite pcDuino (A10) and pcDuino v3 (A20) boards.
> The resync happened in b9d59d0 [1] and 3c92cca [2], after which u-boot
> doesn't rec
On Sun, Dec 30, 2018 at 1:25 AM Nikolai Zhubr wrote:
>
> 29.12.2018 21:51, Jagan Teki:
> > On Wed, Dec 26, 2018 at 4:20 PM Nikolai Zhubr wrote:
> >>
> >> Add Hynix H27UBG8T2BTR nand chip identification.
> >> These chips are sometimes present in e.g. older
On Tue, Jan 1, 2019 at 12:01 AM Marek Vasut wrote:
>
> On 12/31/18 5:59 PM, Jagan Teki wrote:
> > Now clock and reset drivers are available for respective
> > SoC's so use clk and reset ops on phy driver.
> >
> > Cc: Marek Vasut
> > Signed-off-by
Add Allwinner sun6i SPI driver for A31, H3/H5 an A64.
Cc: Fahad Sadah
Signed-off-by: Jagan Teki
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile| 1 +
drivers/spi/sun6i_spi.c | 398
3 files changed, 405 insertions(+)
create mode 100644
Now Allwinner platform is all set to use Generic USB
controller drivers, so remove the legacy sunxi drivers.
Cc: Marek Vasut
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/usb/host/Makefile | 2 -
drivers/usb/host/ehci-sunxi.c | 204 -
drivers
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
configs/A10-OLinuXino-Lime_defconfig | 1 +
configs/A10s-OLinuXino-M_defconfig| 1 +
configs/A13-OLinuXinoM_defconfig | 1 +
configs/A13-OLinuXino_defconfig | 1 +
configs/A20-OLinuXino-Lime2
Implement SPI AHB and MOD clocks for Allwinner A10/A20
and A10s/A13 SoC clock drivers via ccu clock gate table.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a10.c | 9 +
drivers/clk/sunxi/clk_a10s.c | 7 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/clk/sunxi
Add CLK support to enable AHB and MOD SPI clocks
on sun4i_spi driver.
Signed-off-by: Jagan Teki
---
drivers/spi/sun4i_spi.c | 46 +++--
1 file changed, 40 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index
Implement SPI AHB, MOD clocks and resets for Allwinner A64.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a64.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 1d0cd98183..09ff871aee 100644
--- a/drivers/clk/sunxi
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